From patchwork Tue Jan 14 11:04:21 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Srinivas KANDAGATLA X-Patchwork-Id: 3485301 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 6440A9F169 for ; Tue, 14 Jan 2014 11:10:35 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6A19C201F7 for ; Tue, 14 Jan 2014 11:10:34 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 671C5201E9 for ; Tue, 14 Jan 2014 11:10:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751609AbaANLKN (ORCPT ); Tue, 14 Jan 2014 06:10:13 -0500 Received: from eu1sys200aog111.obsmtp.com ([207.126.144.131]:34506 "EHLO eu1sys200aog111.obsmtp.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751503AbaANLKM (ORCPT ); Tue, 14 Jan 2014 06:10:12 -0500 Received: from beta.dmz-eu.st.com ([164.129.1.35]) (using TLSv1) by eu1sys200aob111.postini.com ([207.126.147.11]) with SMTP ID DSNKUtUbDvfz+DudjkW4Z7lWLS/ASo5B0nYH@postini.com; Tue, 14 Jan 2014 11:10:12 UTC Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id EC93012A; Tue, 14 Jan 2014 11:09:07 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 5451215C1D; Tue, 14 Jan 2014 10:56:06 +0000 (GMT) Received: from localhost (10.65.51.147) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.123.3; Tue, 14 Jan 2014 12:09:53 +0100 From: To: Cc: Mauro Carvalho Chehab , , Srinivas Kandagatla Subject: [PATCH v1] media: st-rc: Add reset support Date: Tue, 14 Jan 2014 11:04:21 +0000 Message-ID: <1389697461-21001-1-git-send-email-srinivas.kandagatla@st.com> X-Mailer: git-send-email 1.7.6.5 MIME-Version: 1.0 X-Originating-IP: [10.65.51.147] Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-7.0 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Srinivas Kandagatla Some of the SOCs hold the IRB IP in softreset state by default. For this IP to work driver needs to bring it out of softreset. This patch adds support to reset the IP via reset framework. Without this patch the driver can not work with SoCs which holds the IP in softreset. Signed-off-by: Srinivas Kandagatla --- drivers/media/rc/st_rc.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/drivers/media/rc/st_rc.c b/drivers/media/rc/st_rc.c index 65120c2..8f0cddb 100644 --- a/drivers/media/rc/st_rc.c +++ b/drivers/media/rc/st_rc.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include @@ -28,6 +29,7 @@ struct st_rc_device { int sample_mult; int sample_div; bool rxuhfmode; + struct reset_control *rstc; }; /* Registers */ @@ -161,6 +163,10 @@ static void st_rc_hardware_init(struct st_rc_device *dev) unsigned int rx_max_symbol_per = MAX_SYMB_TIME; unsigned int rx_sampling_freq_div; + /* Enable the IP */ + if (dev->rstc) + reset_control_deassert(dev->rstc); + clk_prepare_enable(dev->sys_clock); baseclock = clk_get_rate(dev->sys_clock); @@ -271,6 +277,11 @@ static int st_rc_probe(struct platform_device *pdev) else rc_dev->rx_base = rc_dev->base; + + rc_dev->rstc = reset_control_get(dev, NULL); + if (IS_ERR(rc_dev->rstc)) + rc_dev->rstc = NULL; + rc_dev->dev = dev; platform_set_drvdata(pdev, rc_dev); st_rc_hardware_init(rc_dev); @@ -338,6 +349,8 @@ static int st_rc_suspend(struct device *dev) writel(0x00, rc_dev->rx_base + IRB_RX_EN); writel(0x00, rc_dev->rx_base + IRB_RX_INT_EN); clk_disable_unprepare(rc_dev->sys_clock); + if (rc_dev->rstc) + reset_control_assert(rc_dev->rstc); } return 0;