From patchwork Sat Jun 7 21:56:22 2014 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Steve Longerbeam X-Patchwork-Id: 4316111 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.19.201]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 78BD39F170 for ; Sat, 7 Jun 2014 21:57:29 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 6BF6B20225 for ; Sat, 7 Jun 2014 21:57:28 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 39C1720222 for ; Sat, 7 Jun 2014 21:57:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753352AbaFGV5X (ORCPT ); Sat, 7 Jun 2014 17:57:23 -0400 Received: from mail-pd0-f172.google.com ([209.85.192.172]:42314 "EHLO mail-pd0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753291AbaFGV5V (ORCPT ); Sat, 7 Jun 2014 17:57:21 -0400 Received: by mail-pd0-f172.google.com with SMTP id fp1so3830138pdb.17 for ; Sat, 07 Jun 2014 14:57:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20120113; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=TaHJm9OMJAOBpO1FeMyex4onKxg8c9fMUNv+5tsv1TE=; b=adnfje1h6JTy8ciYRco54GVPwZz4btXYdF+Zs2YT1V3HINvoEv3qsIvrBDO5+Bnvua 6Uyl9CmqvNXwyDqOKIF6Qgu4yijTact32njWk54RYom5gsIthXXx2YeefW6k7IFl3a5w aK2Zze2jBF84ejd8SxbOPpdOE9IdVQ91F2J76tJyKVQ+xHOLfK95DRj0pNrbXgZNSJ8W 3HsnUj1Njj0OqKdkXORjf0bWHfeGmtlw6RRHfydy/mldyof6Z8U3ieCftb+fAb8YSX67 4Z7LVqoztOHMm1blZi6eqiT6QOhLrHmGaVXxaSfS85+oH9s6t6zVyT72rv1TwcBW1CuW 3cIw== X-Received: by 10.68.237.228 with SMTP id vf4mr2552836pbc.131.1402178240748; Sat, 07 Jun 2014 14:57:20 -0700 (PDT) Received: from slongerb-fremont-linux.mgc.mentorg.com (c-98-248-118-71.hsd1.ca.comcast.net. [98.248.118.71]) by mx.google.com with ESMTPSA id fx5sm52769595pbb.62.2014.06.07.14.57.19 for (version=TLSv1.1 cipher=ECDHE-RSA-RC4-SHA bits=128/128); Sat, 07 Jun 2014 14:57:20 -0700 (PDT) From: Steve Longerbeam X-Google-Original-From: Steve Longerbeam To: linux-media@vger.kernel.org Cc: Steve Longerbeam Subject: [PATCH 20/43] imx-drm: ipu-v3: Add idmac channel linking support Date: Sat, 7 Jun 2014 14:56:22 -0700 Message-Id: <1402178205-22697-21-git-send-email-steve_longerbeam@mentor.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1402178205-22697-1-git-send-email-steve_longerbeam@mentor.com> References: <1402178205-22697-1-git-send-email-steve_longerbeam@mentor.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-7.4 required=5.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, T_DKIM_INVALID, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add idmac channel linking/unlinking functions for specific IPU client use cases. The following linkings are currently needed: - ipu_link_prp_enc_rot_enc(): Link IPUV3_CHANNEL_IC_PRP_ENC_MEM to IPUV3_CHANNEL_MEM_ROT_ENC. - ipu_link_prpvf_rot_prpvf(): Links IPUV3_CHANNEL_IC_PRP_VF_MEM to IPUV3_CHANNEL_MEM_ROT_VF. - ipu_link_pp_rot_pp(): Links IPUV3_CHANNEL_IC_PP_MEM to IPUV3_CHANNEL_MEM_ROT_PP. Signed-off-by: Steve Longerbeam --- drivers/staging/imx-drm/ipu-v3/ipu-common.c | 159 +++++++++++++++++++++++++++ drivers/staging/imx-drm/ipu-v3/ipu-prv.h | 58 ++++++++++ include/linux/platform_data/imx-ipu-v3.h | 7 ++ 3 files changed, 224 insertions(+) diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-common.c b/drivers/staging/imx-drm/ipu-v3/ipu-common.c index dfa6cf3..de66d02 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-common.c +++ b/drivers/staging/imx-drm/ipu-v3/ipu-common.c @@ -973,6 +973,165 @@ void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num) } EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer); +/* + * Links IPUV3_CHANNEL_IC_PRP_ENC_MEM to IPUV3_CHANNEL_MEM_ROT_ENC + */ +int ipu_link_prp_enc_rot_enc(struct ipu_soc *ipu) +{ + unsigned long flags; + u32 fs_proc_flow1; + u32 fs_proc_flow2; + + spin_lock_irqsave(&ipu->lock, flags); + + fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1); + fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2); + + fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= (0x07 << FS_PRPENC_ROT_SRC_SEL_OFFSET); + + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + fs_proc_flow2 |= (0x01 << FS_PRPENC_DEST_SEL_OFFSET); + + ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1); + ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2); + + spin_unlock_irqrestore(&ipu->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(ipu_link_prp_enc_rot_enc); + +/* + * Unlinks IPUV3_CHANNEL_IC_PRP_ENC_MEM from IPUV3_CHANNEL_MEM_ROT_ENC + */ +int ipu_unlink_prp_enc_rot_enc(struct ipu_soc *ipu) +{ + unsigned long flags; + u32 fs_proc_flow1; + u32 fs_proc_flow2; + + spin_lock_irqsave(&ipu->lock, flags); + + fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1); + fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2); + + fs_proc_flow1 &= ~FS_PRPENC_ROT_SRC_SEL_MASK; + fs_proc_flow2 &= ~FS_PRPENC_DEST_SEL_MASK; + + ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1); + ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2); + + spin_unlock_irqrestore(&ipu->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(ipu_unlink_prp_enc_rot_enc); + +/* + * Links IPUV3_CHANNEL_IC_PRP_VF_MEM to IPUV3_CHANNEL_MEM_ROT_VF + */ +int ipu_link_prpvf_rot_prpvf(struct ipu_soc *ipu) +{ + unsigned long flags; + u32 fs_proc_flow1; + u32 fs_proc_flow2; + + spin_lock_irqsave(&ipu->lock, flags); + + fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1); + fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2); + + fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= (0x08 << FS_PRPVF_ROT_SRC_SEL_OFFSET); + + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + fs_proc_flow2 |= (0x01 << FS_PRPVF_DEST_SEL_OFFSET); + + ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1); + ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2); + + spin_unlock_irqrestore(&ipu->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(ipu_link_prpvf_rot_prpvf); + +/* + * Unlinks IPUV3_CHANNEL_IC_PRP_VF_MEM from IPUV3_CHANNEL_MEM_ROT_VF + */ +int ipu_unlink_prpvf_rot_prpvf(struct ipu_soc *ipu) +{ + unsigned long flags; + u32 fs_proc_flow1; + u32 fs_proc_flow2; + + spin_lock_irqsave(&ipu->lock, flags); + + fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1); + fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2); + + fs_proc_flow1 &= ~FS_PRPVF_ROT_SRC_SEL_MASK; + fs_proc_flow2 &= ~FS_PRPVF_DEST_SEL_MASK; + + ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1); + ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2); + + spin_unlock_irqrestore(&ipu->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(ipu_unlink_prpvf_rot_prpvf); + +/* + * Links IPUV3_CHANNEL_IC_PP_MEM to IPUV3_CHANNEL_MEM_ROT_PP + */ +int ipu_link_pp_rot_pp(struct ipu_soc *ipu) +{ + unsigned long flags; + u32 fs_proc_flow1; + u32 fs_proc_flow2; + + spin_lock_irqsave(&ipu->lock, flags); + + fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1); + fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2); + + fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK; + fs_proc_flow1 |= (0x05 << FS_PP_ROT_SRC_SEL_OFFSET); + + fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK; + fs_proc_flow2 |= (0x03 << FS_PP_DEST_SEL_OFFSET); + + ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1); + ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2); + + spin_unlock_irqrestore(&ipu->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(ipu_link_pp_rot_pp); + +/* + * Unlinks IPUV3_CHANNEL_IC_PP_MEM from IPUV3_CHANNEL_MEM_ROT_PP + */ +int ipu_unlink_pp_rot_pp(struct ipu_soc *ipu) +{ + unsigned long flags; + u32 fs_proc_flow1; + u32 fs_proc_flow2; + + spin_lock_irqsave(&ipu->lock, flags); + + fs_proc_flow1 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW1); + fs_proc_flow2 = ipu_cm_read(ipu, IPU_FS_PROC_FLOW2); + + fs_proc_flow1 &= ~FS_PP_ROT_SRC_SEL_MASK; + fs_proc_flow2 &= ~FS_PP_DEST_SEL_MASK; + + ipu_cm_write(ipu, fs_proc_flow1, IPU_FS_PROC_FLOW1); + ipu_cm_write(ipu, fs_proc_flow2, IPU_FS_PROC_FLOW2); + + spin_unlock_irqrestore(&ipu->lock, flags); + return 0; +} +EXPORT_SYMBOL_GPL(ipu_unlink_pp_rot_pp); + int ipu_idmac_enable_channel(struct ipuv3_channel *channel) { struct ipu_soc *ipu = channel->ipu; diff --git a/drivers/staging/imx-drm/ipu-v3/ipu-prv.h b/drivers/staging/imx-drm/ipu-v3/ipu-prv.h index 446ed20..d10e624 100644 --- a/drivers/staging/imx-drm/ipu-v3/ipu-prv.h +++ b/drivers/staging/imx-drm/ipu-v3/ipu-prv.h @@ -83,6 +83,64 @@ struct ipu_soc; #define IPU_DI0_COUNTER_RELEASE (1 << 24) #define IPU_DI1_COUNTER_RELEASE (1 << 25) +#define FS_PRPENC_ROT_SRC_SEL_MASK (0xf << 0) +#define FS_PRPENC_ROT_SRC_SEL_OFFSET 0 +#define FS_PRPVF_ROT_SRC_SEL_MASK (0xf << 8) +#define FS_PRPVF_ROT_SRC_SEL_OFFSET 8 +#define FS_PP_ROT_SRC_SEL_MASK (0xf << 16) +#define FS_PP_ROT_SRC_SEL_OFFSET 16 +#define FS_PP_SRC_SEL_MASK (0xf << 12) +#define FS_PP_SRC_SEL_OFFSET 12 +#define FS_PP_SRC_SEL_VDOA (1 << 15) +#define FS_PRP_SRC_SEL_MASK (0xf << 24) +#define FS_PRP_SRC_SEL_OFFSET 24 +#define FS_VF_IN_VALID (1 << 31) +#define FS_ENC_IN_VALID (1 << 30) +#define FS_VDI_SRC_SEL_MASK (0x3 << 28) +#define FS_VDI_SRC_SEL_VDOA (0x2 << 28) +#define FS_VDOA_DEST_SEL_MASK (0x3 << 16) +#define FS_VDOA_DEST_SEL_VDI (0x2 << 16) +#define FS_VDOA_DEST_SEL_IC (0x1 << 16) +#define FS_VDI_SRC_SEL_OFFSET 28 + +#define FS_PRPENC_DEST_SEL_MASK (0xf << 0) +#define FS_PRPENC_DEST_SEL_OFFSET 0 +#define FS_PRPVF_DEST_SEL_MASK (0xf << 4) +#define FS_PRPVF_DEST_SEL_OFFSET 4 +#define FS_PRPVF_ROT_DEST_SEL_MASK (0xf << 8) +#define FS_PRPVF_ROT_DEST_SEL_OFFSET 8 +#define FS_PP_DEST_SEL_MASK (0xf << 12) +#define FS_PP_DEST_SEL_OFFSET 12 +#define FS_PP_ROT_DEST_SEL_MASK (0xf << 16) +#define FS_PP_ROT_DEST_SEL_OFFSET 16 +#define FS_PRPENC_ROT_DEST_SEL_MASK (0xf << 20) +#define FS_PRPENC_ROT_DEST_SEL_OFFSET 20 + +#define FS_SMFC0_DEST_SEL_MASK (0xf << 0) +#define FS_SMFC0_DEST_SEL_OFFSET 0 +#define FS_SMFC1_DEST_SEL_MASK (0x7 << 4) +#define FS_SMFC1_DEST_SEL_OFFSET 4 +#define FS_SMFC2_DEST_SEL_MASK (0xf << 7) +#define FS_SMFC2_DEST_SEL_OFFSET 7 +#define FS_SMFC3_DEST_SEL_MASK (0x7 << 11) +#define FS_SMFC3_DEST_SEL_OFFSET 11 + +#define FS_DC1_SRC_SEL_MASK (0xf << 20) +#define FS_DC1_SRC_SEL_OFFSET 20 +#define FS_DC2_SRC_SEL_MASK (0xf << 16) +#define FS_DC2_SRC_SEL_OFFSET 16 +#define FS_DP_SYNC0_SRC_SEL_MASK (0xf << 0) +#define FS_DP_SYNC0_SRC_SEL_OFFSET 0 +#define FS_DP_SYNC1_SRC_SEL_MASK (0xf << 4) +#define FS_DP_SYNC1_SRC_SEL_OFFSET 4 +#define FS_DP_ASYNC0_SRC_SEL_MASK (0xf << 8) +#define FS_DP_ASYNC0_SRC_SEL_OFFSET 8 +#define FS_DP_ASYNC1_SRC_SEL_MASK (0xf << 12) +#define FS_DP_ASYNC1_SRC_SEL_OFFSET 12 + +#define FS_AUTO_REF_PER_MASK 0 +#define FS_AUTO_REF_PER_OFFSET 16 + #define IPU_IDMAC_REG(offset) (offset) #define IDMAC_CONF IPU_IDMAC_REG(0x0000) diff --git a/include/linux/platform_data/imx-ipu-v3.h b/include/linux/platform_data/imx-ipu-v3.h index 949beec..75a6a5d 100644 --- a/include/linux/platform_data/imx-ipu-v3.h +++ b/include/linux/platform_data/imx-ipu-v3.h @@ -205,6 +205,13 @@ int ipu_idmac_current_buffer(struct ipuv3_channel *channel); void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable); int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts); +int ipu_link_prp_enc_rot_enc(struct ipu_soc *ipu); +int ipu_unlink_prp_enc_rot_enc(struct ipu_soc *ipu); +int ipu_link_prpvf_rot_prpvf(struct ipu_soc *ipu); +int ipu_unlink_prpvf_rot_prpvf(struct ipu_soc *ipu); +int ipu_link_pp_rot_pp(struct ipu_soc *ipu); +int ipu_unlink_pp_rot_pp(struct ipu_soc *ipu); + /* * IPU Display Controller (dc) functions */