@@ -5,10 +5,11 @@ Coda codec IPs are present in i.MX SoCs in various versions,
called VPU (Video Processing Unit).
Required properties:
-- compatible : should be "fsl,<chip>-src" for i.MX SoCs:
- (a) "fsl,imx27-vpu" for CodaDx6 present in i.MX27
- (b) "fsl,imx53-vpu" for CODA7541 present in i.MX53
- (c) "fsl,imx6q-vpu" for CODA960 present in i.MX6q
+- compatible : should be "fsl,<chip>-src", "cnm,coda<model>" for i.MX SoCs:
+ (a) "fsl,imx27-vpu", "cnm,codadx6" for CodaDx6 present in i.MX27
+ (b) "fsl,imx53-vpu", "cnm,coda7541" for CODA7541 present in i.MX53
+ (c) "fsl,imx6q-vpu", "cnm,coda960" for CODA960 present in i.MX6Q/D
+ (d) "fsl,imx6dl-vpu", "cnm,coda960" for CODA960 present in i.MX6DL/S
- reg: should be register base and length as documented in the
SoC reference manual
- interrupts : Should contain the VPU interrupt. For CODA960,
@@ -21,7 +22,7 @@ Required properties:
Example:
vpu: vpu@63ff4000 {
- compatible = "fsl,imx53-vpu";
+ compatible = "fsl,imx53-vpu", "cnm,coda7541";
reg = <0x63ff4000 0x1000>;
interrupts = <9>;
clocks = <&clks 63>, <&clks 63>;