From patchwork Fri Dec 11 09:55:39 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "tiffany.lin" X-Patchwork-Id: 7827941 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 057889F387 for ; Fri, 11 Dec 2015 09:59:01 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 1BE912057E for ; Fri, 11 Dec 2015 09:59:00 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 15E6720562 for ; Fri, 11 Dec 2015 09:58:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1754739AbbLKJ6e (ORCPT ); Fri, 11 Dec 2015 04:58:34 -0500 Received: from mailgw01.mediatek.com ([210.61.82.183]:38647 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1754576AbbLKJ4E (ORCPT ); Fri, 11 Dec 2015 04:56:04 -0500 X-Listener-Flag: 11101 Received: from mtkhts07.mediatek.inc [(172.21.101.69)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 560767726; Fri, 11 Dec 2015 17:55:56 +0800 Received: from mtkslt302.mediatek.inc (10.21.14.115) by mtkhts07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Fri, 11 Dec 2015 17:55:55 +0800 From: Tiffany Lin To: , Rob Herring , Pawel Moll , Mark Rutland , Ian Campbell , Kumar Gala , Catalin Marinas , Will Deacon , Mauro Carvalho Chehab , Matthias Brugger , Daniel Kurtz , Hans Verkuil , Laurent Pinchart , Sakari Ailus , Mikhail Ulyanov , Fabien Dessenne , Arnd Bergmann , Darren Etheridge , Peter Griffin , Benoit Parrot CC: Tiffany Lin , Andrew-CT Chen , Eddie Huang , Yingjoe Chen , James Liao , Hongzhou Yang , Daniel Hsiao , , , , , , Subject: [PATCH v2 4/8] dt-bindings: Add a binding for Mediatek Video Encoder Date: Fri, 11 Dec 2015 17:55:39 +0800 Message-ID: <1449827743-22895-5-git-send-email-tiffany.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1449827743-22895-1-git-send-email-tiffany.lin@mediatek.com> References: <1449827743-22895-1-git-send-email-tiffany.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a DT binding documentation of Video Encoder for the MT8173 SoC from Mediatek. Signed-off-by: Tiffany Lin Acked-by: Rob Herring --- .../devicetree/bindings/media/mediatek-vcodec.txt | 58 ++++++++++++++++++++ 1 file changed, 58 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-vcodec.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt new file mode 100644 index 0000000..510cd81 --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -0,0 +1,58 @@ +Mediatek Video Codec + +Mediatek Video Codec is the video codec hw present in Mediatek SoCs which +supports high resolution encoding functionalities. + +Required properties: +- compatible : "mediatek,mt8173-vcodec-enc" for encoder +- reg : Physical base address of the video codec registers and length of + memory mapped region. +- interrupts : interrupt number to the cpu. +- mediatek,larb : must contain the local arbiters in the current Socs. +- clocks : list of clock specifiers, corresponding to entries in + the clock-names property; +- clock-names: must contain "vencpll", "venc_lt_sel", "vcodecpll_370p5_ck" +- iommus : list of iommus specifiers should be enabled for hw encode. + There are 2 cells needed to enable/disable iommu. + The first one is local arbiter index(larbid), and the other is port + index(portid) within local arbiter. Specifies the larbid and portid + as defined in dt-binding/memory/mt8173-larb-port.h. +- mediatek,vpu : the node of video processor unit + +Example: +vcodec_enc: vcodec@0x18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>, /*VENC_SYS*/ + <0 0x19002000 0 0x1000>; /*VENC_LT_SYS*/ + interrupts = , + ; + larb = <&larb3>, + <&larb5>; + iommus = <&iommu M4U_LARB3_ID M4U_PORT_VENC_RCPU>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REC>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_BSDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_LARB3_ID M4U_PORT_VENC_NBM_WDMA>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_LARB5_ID M4U_PORT_VENC_REC_CHROMA_SET2>; + vpu = <&vpu>; + clocks = <&apmixedsys CLK_APMIXED_VENCPLL>, + <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_VCODECPLL_370P5>; + clock-names = "vencpll", + "venc_lt_sel", + "vcodecpll_370p5_ck"; + };