From patchwork Tue Feb 23 08:11:21 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "tiffany.lin" X-Patchwork-Id: 8388771 Return-Path: X-Original-To: patchwork-linux-media@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork2.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork2.web.kernel.org (Postfix) with ESMTP id 933EAC0554 for ; Tue, 23 Feb 2016 08:14:49 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id BEA6C203DF for ; Tue, 23 Feb 2016 08:14:48 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id B6222206B8 for ; Tue, 23 Feb 2016 08:14:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932729AbcBWILa (ORCPT ); Tue, 23 Feb 2016 03:11:30 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:9087 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1756930AbcBWIL3 (ORCPT ); Tue, 23 Feb 2016 03:11:29 -0500 Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1608862453; Tue, 23 Feb 2016 16:11:24 +0800 Received: from localhost.localdomain (10.21.14.115) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Tue, 23 Feb 2016 16:11:24 +0800 From: Tiffany Lin To: Hans Verkuil , , Rob Herring , Mauro Carvalho Chehab , Matthias Brugger , Daniel Kurtz , Pawel Osciak CC: Eddie Huang , Yingjoe Chen , , , , , , , , Tiffany Lin Subject: [PATCH v5 8/8] arm64: dts: mediatek: Add Video Encoder for MT8173 Date: Tue, 23 Feb 2016 16:11:21 +0800 Message-ID: <1456215081-16858-9-git-send-email-tiffany.lin@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1456215081-16858-8-git-send-email-tiffany.lin@mediatek.com> References: <1456215081-16858-1-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-2-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-3-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-4-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-5-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-6-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-7-git-send-email-tiffany.lin@mediatek.com> <1456215081-16858-8-git-send-email-tiffany.lin@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Spam-Status: No, score=-6.9 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_HI, RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add video encoder node for MT8173 Signed-off-by: Tiffany Lin --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 39 ++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 5b0b38a..26aeffe 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1150,6 +1150,45 @@ clock-names = "apb", "smi"; }; + vcodec_enc: vcodec@18002000 { + compatible = "mediatek,mt8173-vcodec-enc"; + reg = <0 0x18002000 0 0x1000>, /* VENC_SYS */ + <0 0x19002000 0 0x1000>; /* VENC_LT_SYS */ + interrupts = , + ; + mediatek,larb = <&larb3>, + <&larb5>; + iommus = <&iommu M4U_PORT_VENC_RCPU>, + <&iommu M4U_PORT_VENC_REC>, + <&iommu M4U_PORT_VENC_BSDMA>, + <&iommu M4U_PORT_VENC_SV_COMV>, + <&iommu M4U_PORT_VENC_RD_COMV>, + <&iommu M4U_PORT_VENC_CUR_LUMA>, + <&iommu M4U_PORT_VENC_CUR_CHROMA>, + <&iommu M4U_PORT_VENC_REF_LUMA>, + <&iommu M4U_PORT_VENC_REF_CHROMA>, + <&iommu M4U_PORT_VENC_NBM_RDMA>, + <&iommu M4U_PORT_VENC_NBM_WDMA>, + <&iommu M4U_PORT_VENC_RCPU_SET2>, + <&iommu M4U_PORT_VENC_REC_FRM_SET2>, + <&iommu M4U_PORT_VENC_BSDMA_SET2>, + <&iommu M4U_PORT_VENC_SV_COMA_SET2>, + <&iommu M4U_PORT_VENC_RD_COMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_LUMA_SET2>, + <&iommu M4U_PORT_VENC_CUR_CHROMA_SET2>, + <&iommu M4U_PORT_VENC_REF_LUMA_SET2>, + <&iommu M4U_PORT_VENC_REC_CHROMA_SET2>; + mediatek,vpu = <&vpu>; + clocks = <&topckgen CLK_TOP_VENCPLL_D2>, + <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_UNIVPLL1_D2>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + clock-names = "venc_sel_src", + "venc_sel", + "venc_lt_sel_src", + "venc_lt_sel"; + }; + vencltsys: clock-controller@19000000 { compatible = "mediatek,mt8173-vencltsys", "syscon"; reg = <0 0x19000000 0 0x1000>;