From patchwork Wed Dec 21 08:10:37 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Ramesh Shanmugasundaram X-Patchwork-Id: 9482733 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 790BB60237 for ; Wed, 21 Dec 2016 08:25:54 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 674C728179 for ; Wed, 21 Dec 2016 08:25:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5B757282F5; Wed, 21 Dec 2016 08:25:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C0D8328179 for ; Wed, 21 Dec 2016 08:25:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753028AbcLUIZu (ORCPT ); Wed, 21 Dec 2016 03:25:50 -0500 Received: from relmlor1.renesas.com ([210.160.252.171]:43763 "EHLO relmlie4.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1750762AbcLUIZs (ORCPT ); Wed, 21 Dec 2016 03:25:48 -0500 X-Greylist: delayed 304 seconds by postgrey-1.27 at vger.kernel.org; Wed, 21 Dec 2016 03:25:39 EST Received: from unknown (HELO relmlir3.idc.renesas.com) ([10.200.68.153]) by relmlie4.idc.renesas.com with ESMTP; 21 Dec 2016 17:20:44 +0900 Received: from relmlac2.idc.renesas.com (relmlac2.idc.renesas.com [10.200.69.22]) by relmlir3.idc.renesas.com (Postfix) with ESMTP id 1D112617F0; Wed, 21 Dec 2016 17:20:44 +0900 (JST) Received: by relmlac2.idc.renesas.com (Postfix, from userid 0) id 0756828070; Wed, 21 Dec 2016 17:20:43 +0900 (JST) Received: from relmlac2.idc.renesas.com (localhost [127.0.0.1]) by relmlac2.idc.renesas.com (Postfix) with ESMTP id E93BC2806F; Wed, 21 Dec 2016 17:20:43 +0900 (JST) Received: from relmlii2.idc.renesas.com [10.200.68.66] by relmlac2.idc.renesas.com with ESMTP id TAD18287; Wed, 21 Dec 2016 17:20:43 +0900 X-IronPort-AV: E=Sophos;i="5.33,382,1477926000"; d="scan'208";a="229279710" Received: from unknown (HELO localhost.localdomain) ([172.29.43.62]) by relmlii2.idc.renesas.com with ESMTP; 21 Dec 2016 17:20:40 +0900 From: Ramesh Shanmugasundaram To: robh+dt@kernel.org, mark.rutland@arm.com, mchehab@kernel.org, hverkuil@xs4all.nl, sakari.ailus@linux.intel.com, crope@iki.fi Cc: chris.paterson2@renesas.com, laurent.pinchart@ideasonboard.com, geert+renesas@glider.be, linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-renesas-soc@vger.kernel.org, Ramesh Shanmugasundaram Subject: [PATCH v2 6/7] dt-bindings: media: Add Renesas R-Car DRIF binding Date: Wed, 21 Dec 2016 08:10:37 +0000 Message-Id: <1482307838-47415-7-git-send-email-ramesh.shanmugasundaram@bp.renesas.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1482307838-47415-1-git-send-email-ramesh.shanmugasundaram@bp.renesas.com> References: <1478706284-59134-1-git-send-email-ramesh.shanmugasundaram@bp.renesas.com> <1482307838-47415-1-git-send-email-ramesh.shanmugasundaram@bp.renesas.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add binding documentation for Renesas R-Car Digital Radio Interface (DRIF) controller. Signed-off-by: Ramesh Shanmugasundaram --- .../devicetree/bindings/media/renesas,drif.txt | 202 +++++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/renesas,drif.txt diff --git a/Documentation/devicetree/bindings/media/renesas,drif.txt b/Documentation/devicetree/bindings/media/renesas,drif.txt new file mode 100644 index 0000000..1f3feaf --- /dev/null +++ b/Documentation/devicetree/bindings/media/renesas,drif.txt @@ -0,0 +1,202 @@ +Renesas R-Car Gen3 Digital Radio Interface controller (DRIF) +------------------------------------------------------------ + +R-Car Gen3 DRIF is a SPI like receive only slave device. A general +representation of DRIF interfacing with a master device is shown below. + ++---------------------+ +---------------------+ +| |-----SCK------->|CLK | +| Master |-----SS-------->|SYNC DRIFn (slave) | +| |-----SD0------->|D0 | +| |-----SD1------->|D1 | ++---------------------+ +---------------------+ + +As per datasheet, each DRIF channel (drifn) is made up of two internal +channels (drifn0 & drifn1). These two internal channels share the common +CLK & SYNC. Each internal channel has its own dedicated resources like +irq, dma channels, address space & clock. This internal split is not +visible to the external master device. + +The device tree model represents each internal channel as a separate node. +The internal channels sharing the CLK & SYNC are tied together by their +phandles using a new property called "renesas,bonding". For the rest of +the documentation, unless explicitly stated, the word channel implies an +internal channel. + +When both internal channels are enabled they need to be managed together +as one (i.e.) they cannot operate alone as independent devices. Out of the +two, one of them needs to act as a primary device that accepts common +properties of both the internal channels. This channel is identified by a +new property called "renesas,primary-bond". + +To summarize, + - When both the internal channels that are bonded together are enabled, + the zeroth channel is selected as primary-bond. This channels accepts + properties common to all the members of the bond. + - When only one of the bonded channels need to be enabled, the property + "renesas,bonding" or "renesas,primary-bond" will have no effect. That + enabled channel can act alone as any other independent device. + +Required properties of an internal channel: +------------------------------------------- +- compatible: "renesas,r8a7795-drif" if DRIF controller is a part of R8A7795 SoC. + "renesas,rcar-gen3-drif" for a generic R-Car Gen3 compatible device. + When compatible with the generic version, nodes must list the + SoC-specific version corresponding to the platform first + followed by the generic version. +- reg: offset and length of that channel. +- interrupts: associated with that channel. +- clocks: phandle and clock specifier of that channel. +- clock-names: clock input name string: "fck". +- dmas: phandles to the DMA channels. +- dma-names: names of the DMA channel: "rx". +- renesas,bonding: phandle to the other channel. + +Optional properties of an internal channel: +------------------------------------------- +- power-domains: phandle to the respective power domain. + +Required properties of an internal channel when: + - It is the only enabled channel of the bond (or) + - If it acts as primary among enabled bonds +-------------------------------------------------------- +- pinctrl-0: pin control group to be used for this channel. +- pinctrl-names: must be "default". +- renesas,primary-bond: empty property indicating the channel acts as primary + among the bonded channels. +- port: child port node of a channel that defines the local and remote + endpoints. The remote endpoint is assumed to be a third party tuner + device endpoint. + +Optional properties of an internal channel when: + - It is the only enabled channel of the bond (or) + - If it acts as primary among enabled bonds +-------------------------------------------------------- +- renesas,syncmd : sync mode + 0 (Frame start sync pulse mode. 1-bit width pulse + indicates start of a frame) + 1 (L/R sync or I2S mode) (default) +- renesas,lsb-first : empty property indicates lsb bit is received first. + When not defined msb bit is received first (default) +- renesas,syncac-active: Indicates sync signal polarity, 0/1 for low/high + respectively. The default is 1 (active high) +- renesas,dtdl : delay between sync signal and start of reception. + The possible values are represented in 0.5 clock + cycle units and the range is 0 to 4. The default + value is 2 (i.e.) 1 clock cycle delay. +- renesas,syncdl : delay between end of reception and sync signal edge. + The possible values are represented in 0.5 clock + cycle units and the range is 0 to 4 & 6. The default + value is 0 (i.e.) no delay. + +Example +-------- + +SoC common dtsi file + + drif00: rif@e6f40000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f40000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 515>; + clock-names = "fck"; + dmas = <&dmac1 0x20>, <&dmac2 0x20>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + renesas,bonding = <&drif01>; + status = "disabled"; + }; + + drif01: rif@e6f50000 { + compatible = "renesas,r8a7795-drif", + "renesas,rcar-gen3-drif"; + reg = <0 0xe6f50000 0 0x64>; + interrupts = ; + clocks = <&cpg CPG_MOD 514>; + clock-names = "fck"; + dmas = <&dmac1 0x22>, <&dmac2 0x22>; + dma-names = "rx", "rx"; + power-domains = <&sysc R8A7795_PD_ALWAYS_ON>; + renesas,bonding = <&drif00>; + status = "disabled"; + }; + + +Board specific dts file + +(1) Both internal channels enabled, primary-bond = 0 +----------------------------------------------------- + +When interfacing with a third party tuner device with two data pins as shown +below. + ++---------------------+ +---------------------+ +| |-----SCK------->|CLK | +| Master |-----SS-------->|SYNC DRIFn (slave) | +| |-----SD0------->|D0 | +| |-----SD1------->|D1 | ++---------------------+ +---------------------+ + +pfc { + ... + + drif0_pins: drif0 { + groups = "drif0_ctrl_a", "drif0_data0_a", + "drif0_data1_a"; + function = "drif0"; + }; + ... +} + +&drif00 { + pinctrl-0 = <&drif0_pins>; + pinctrl-names = "default"; + renesas,syncac-active = <1>; + renesas,primary-bond; + status = "okay"; + port { + drif0_ep: endpoint { + remote-endpoint = <&tuner_ep>; + }; + }; +}; + +&drif01 { + status = "okay"; +}; + +(2) Internal channel 1 alone is enabled: +---------------------------------------- + +When interfacing with a third party tuner device with one data pin as shown +below. + ++---------------------+ +---------------------+ +| |-----SCK------->|CLK | +| Master |-----SS-------->|SYNC DRIFn (slave) | +| | |D0 (unused) | +| |-----SD-------->|D1 | ++---------------------+ +---------------------+ + +pfc { + ... + + drif0_pins: drif0 { + groups = "drif0_ctrl_a", "drif0_data1_a"; + function = "drif0"; + }; + ... +} + +&drif01 { + pinctrl-0 = <&drif0_pins>; + pinctrl-names = "default"; + renesas,syncac-active = <0>; + status = "okay"; + port { + drif0_ep: endpoint { + remote-endpoint = <&tuner_ep>; + }; + }; +};