From patchwork Thu Jun 22 15:05:40 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Hugues FRUCHET X-Patchwork-Id: 9804629 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 73F256088A for ; Thu, 22 Jun 2017 15:07:43 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 64FBD28562 for ; Thu, 22 Jun 2017 15:07:43 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 59043286BB; Thu, 22 Jun 2017 15:07:43 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F01BE286CA for ; Thu, 22 Jun 2017 15:07:42 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752547AbdFVPGp (ORCPT ); Thu, 22 Jun 2017 11:06:45 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:51585 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751185AbdFVPGm (ORCPT ); Thu, 22 Jun 2017 11:06:42 -0400 Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id v5MF4hQC017418; Thu, 22 Jun 2017 17:06:06 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-.pphosted.com with ESMTP id 2b8d40s3a7-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Thu, 22 Jun 2017 17:06:06 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id DD9E631; Thu, 22 Jun 2017 15:06:03 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id C90F7262E; Thu, 22 Jun 2017 15:06:03 +0000 (GMT) Received: from localhost (10.201.23.73) by webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.339.0; Thu, 22 Jun 2017 17:06:03 +0200 From: Hugues Fruchet To: Sylwester Nawrocki , " H. Nikolaus Schaller" , Guennadi Liakhovetski , Rob Herring , Mark Rutland , Maxime Coquelin , Alexandre Torgue , Mauro Carvalho Chehab , Hans Verkuil CC: , , , , Benjamin Gaignard , Yannick Fertre , Hugues Fruchet Subject: [PATCH v1 4/6] [media] ov9650: use write_array() for resolution sequences Date: Thu, 22 Jun 2017 17:05:40 +0200 Message-ID: <1498143942-12682-5-git-send-email-hugues.fruchet@st.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1498143942-12682-1-git-send-email-hugues.fruchet@st.com> References: <1498143942-12682-1-git-send-email-hugues.fruchet@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.73] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:, , definitions=2017-06-22_06:, , signatures=0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Align resolution sequences on initialization sequence using i2c_rv structure NULL terminated .This add flexibility on resolution sequence size. Document resolution related registers by using corresponding define instead of hexa address/value. Signed-off-by: Hugues Fruchet --- drivers/media/i2c/ov9650.c | 98 ++++++++++++++++++++++++++++++---------------- 1 file changed, 64 insertions(+), 34 deletions(-) diff --git a/drivers/media/i2c/ov9650.c b/drivers/media/i2c/ov9650.c index 4311da6..8b283c9 100644 --- a/drivers/media/i2c/ov9650.c +++ b/drivers/media/i2c/ov9650.c @@ -227,11 +227,16 @@ struct ov965x_ctrls { u8 update; }; +struct i2c_rv { + u8 addr; + u8 value; +}; + struct ov965x_framesize { u16 width; u16 height; u16 max_exp_lines; - const u8 *regs; + const struct i2c_rv *regs; }; struct ov965x_interval { @@ -280,9 +285,11 @@ struct ov965x { u8 apply_frame_fmt; }; -struct i2c_rv { - u8 addr; - u8 value; +struct ov965x_pixfmt { + u32 code; + u32 colorspace; + /* REG_TSLB value, only bits [3:2] may be set. */ + u8 tslb_reg; }; static const struct i2c_rv ov965x_init_regs[] = { @@ -342,30 +349,59 @@ struct i2c_rv { { REG_NULL, 0 } }; -#define NUM_FMT_REGS 14 -/* - * COM7, COM3, COM4, HSTART, HSTOP, HREF, VSTART, VSTOP, VREF, - * EXHCH, EXHCL, ADC, OCOM, OFON - */ -static const u8 frame_size_reg_addr[NUM_FMT_REGS] = { - 0x12, 0x0c, 0x0d, 0x17, 0x18, 0x32, 0x19, 0x1a, 0x03, - 0x2a, 0x2b, 0x37, 0x38, 0x39, -}; - -static const u8 ov965x_sxga_regs[NUM_FMT_REGS] = { - 0x00, 0x00, 0x00, 0x1e, 0xbe, 0xbf, 0x01, 0x81, 0x12, - 0x10, 0x34, 0x81, 0x93, 0x51, +static const struct i2c_rv ov965x_sxga_regs[] = { + { REG_COM7, 0x00 }, + { REG_COM3, 0x00 }, + { REG_COM4, 0x00 }, + { REG_HSTART, 0x1e }, + { REG_HSTOP, 0xbe }, + { 0x32, 0xbf }, + { REG_VSTART, 0x01 }, + { REG_VSTOP, 0x81 }, + { REG_VREF, 0x12 }, + { REG_EXHCH, 0x10 }, + { REG_EXHCL, 0x34 }, + { REG_ADC, 0x81 }, + { REG_ACOM, 0x93 }, + { REG_OFON, 0x51 }, + { REG_NULL, 0 }, }; -static const u8 ov965x_vga_regs[NUM_FMT_REGS] = { - 0x40, 0x04, 0x80, 0x26, 0xc6, 0xed, 0x01, 0x3d, 0x00, - 0x10, 0x40, 0x91, 0x12, 0x43, +static const struct i2c_rv ov965x_vga_regs[] = { + { REG_COM7, 0x40 }, + { REG_COM3, 0x04 }, + { REG_COM4, 0x80 }, + { REG_HSTART, 0x26 }, + { REG_HSTOP, 0xc6 }, + { 0x32, 0xed }, + { REG_VSTART, 0x01 }, + { REG_VSTOP, 0x3d }, + { REG_VREF, 0x00 }, + { REG_EXHCH, 0x10 }, + { REG_EXHCL, 0x40 }, + { REG_ADC, 0x91 }, + { REG_ACOM, 0x12 }, + { REG_OFON, 0x43 }, + { REG_NULL, 0 }, }; /* Determined empirically. */ -static const u8 ov965x_qvga_regs[NUM_FMT_REGS] = { - 0x10, 0x04, 0x80, 0x25, 0xc5, 0xbf, 0x00, 0x80, 0x12, - 0x10, 0x40, 0x91, 0x12, 0x43, +static const struct i2c_rv ov965x_qvga_regs[] = { + { REG_COM7, 0x10 }, + { REG_COM3, 0x04 }, + { REG_COM4, 0x80 }, + { REG_HSTART, 0x25 }, + { REG_HSTOP, 0xc5 }, + { 0x32, 0xbf }, + { REG_VSTART, 0x00 }, + { REG_VSTOP, 0x80 }, + { REG_VREF, 0x12 }, + { REG_EXHCH, 0x10 }, + { REG_EXHCL, 0x40 }, + { REG_ADC, 0x91 }, + { REG_ACOM, 0x12 }, + { REG_OFON, 0x43 }, + { REG_NULL, 0 }, }; static const struct ov965x_framesize ov965x_framesizes[] = { @@ -387,13 +423,6 @@ struct i2c_rv { }, }; -struct ov965x_pixfmt { - u32 code; - u32 colorspace; - /* REG_TSLB value, only bits [3:2] may be set. */ - u8 tslb_reg; -}; - static const struct ov965x_pixfmt ov965x_formats[] = { { MEDIA_BUS_FMT_YUYV8_2X8, V4L2_COLORSPACE_JPEG, 0x00}, { MEDIA_BUS_FMT_YVYU8_2X8, V4L2_COLORSPACE_JPEG, 0x04}, @@ -1268,11 +1297,12 @@ static int ov965x_set_fmt(struct v4l2_subdev *sd, struct v4l2_subdev_pad_config static int ov965x_set_frame_size(struct ov965x *ov965x) { - int i, ret = 0; + int ret = 0; + + v4l2_dbg(1, debug, ov965x->client, "%s\n", __func__); - for (i = 0; ret == 0 && i < NUM_FMT_REGS; i++) - ret = ov965x_write(ov965x->client, frame_size_reg_addr[i], - ov965x->frame_size->regs[i]); + ret = ov965x_write_array(ov965x->client, + ov965x->frame_size->regs); return ret; }