From patchwork Fri Jul 28 23:21:03 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chiranjeevi Rapolu X-Patchwork-Id: 9869657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0F24A60382 for ; Fri, 28 Jul 2017 23:22:55 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DCF8A28648 for ; Fri, 28 Jul 2017 23:22:54 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D003928879; Fri, 28 Jul 2017 23:22:54 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 297F228648 for ; Fri, 28 Jul 2017 23:22:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753199AbdG1XWw (ORCPT ); Fri, 28 Jul 2017 19:22:52 -0400 Received: from mga11.intel.com ([192.55.52.93]:11289 "EHLO mga11.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753095AbdG1XWv (ORCPT ); Fri, 28 Jul 2017 19:22:51 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga102.fm.intel.com with ESMTP/TLS/DHE-RSA-AES256-GCM-SHA384; 28 Jul 2017 16:22:50 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.40,428,1496127600"; d="scan'208";a="998473679" Received: from crapolu-desk.sc.intel.com ([10.3.62.62]) by orsmga003.jf.intel.com with ESMTP; 28 Jul 2017 16:22:50 -0700 From: Chiranjeevi Rapolu To: linux-media@vger.kernel.org, sakari.ailus@linux.intel.com Cc: tfiga@chromium.org, jian.xu.zheng@intel.com, tian.shu.qiu@intel.com, rajmohan.mani@intel.com, hyungwoo.yang@intel.com, Chiranjeevi Rapolu Subject: [PATCH v1] media: ov13858: Increase digital gain granularity, range Date: Fri, 28 Jul 2017 16:21:03 -0700 Message-Id: <1501284063-23771-1-git-send-email-chiranjeevi.rapolu@intel.com> X-Mailer: git-send-email 1.9.1 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Previously, possible digital gains were just 1x, 2x and 4x. These coarse gains were not sufficient in fine-tuning the image capture. Now, digital gain range is [0, 16x] with each step 1/1024, default 1x. This is achieved through OV13858 MWB R/G/B gain controls. Signed-off-by: Chiranjeevi Rapolu --- drivers/media/i2c/ov13858.c | 32 ++++++++++++++++---------------- 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/drivers/media/i2c/ov13858.c b/drivers/media/i2c/ov13858.c index 86550d8..b78e323b 100644 --- a/drivers/media/i2c/ov13858.c +++ b/drivers/media/i2c/ov13858.c @@ -78,13 +78,13 @@ #define OV13858_ANA_GAIN_DEFAULT 0x80 /* Digital gain control */ -#define OV13858_REG_DIGITAL_GAIN 0x350a -#define OV13858_DGTL_GAIN_MASK 0xf3 -#define OV13858_DGTL_GAIN_SHIFT 2 -#define OV13858_DGTL_GAIN_MIN 1 -#define OV13858_DGTL_GAIN_MAX 4 -#define OV13858_DGTL_GAIN_STEP 1 -#define OV13858_DGTL_GAIN_DEFAULT 1 +#define OV13858_REG_B_MWB_GAIN 0x5100 +#define OV13858_REG_G_MWB_GAIN 0x5102 +#define OV13858_REG_R_MWB_GAIN 0x5104 +#define OV13858_DGTL_GAIN_MIN 0 +#define OV13858_DGTL_GAIN_MAX 16384 /* Max = 16 X */ +#define OV13858_DGTL_GAIN_DEFAULT 1024 /* Default gain = 1 X */ +#define OV13858_DGTL_GAIN_STEP 1 /* Each step = 1/1024 */ /* Test Pattern Control */ #define OV13858_REG_TEST_PATTERN 0x4503 @@ -1161,21 +1161,21 @@ static int ov13858_open(struct v4l2_subdev *sd, struct v4l2_subdev_fh *fh) static int ov13858_update_digital_gain(struct ov13858 *ov13858, u32 d_gain) { int ret; - u32 val; - if (d_gain == 3) - return -EINVAL; + ret = ov13858_write_reg(ov13858, OV13858_REG_B_MWB_GAIN, + OV13858_REG_VALUE_16BIT, d_gain); + if (ret) + return ret; - ret = ov13858_read_reg(ov13858, OV13858_REG_DIGITAL_GAIN, - OV13858_REG_VALUE_08BIT, &val); + ret = ov13858_write_reg(ov13858, OV13858_REG_G_MWB_GAIN, + OV13858_REG_VALUE_16BIT, d_gain); if (ret) return ret; - val &= OV13858_DGTL_GAIN_MASK; - val |= (d_gain - 1) << OV13858_DGTL_GAIN_SHIFT; + ret = ov13858_write_reg(ov13858, OV13858_REG_R_MWB_GAIN, + OV13858_REG_VALUE_16BIT, d_gain); - return ov13858_write_reg(ov13858, OV13858_REG_DIGITAL_GAIN, - OV13858_REG_VALUE_08BIT, val); + return ret; } static int ov13858_enable_test_pattern(struct ov13858 *ov13858, u32 pattern)