diff mbox

[v7] rockchip/rga: v4l2 m2m support

Message ID 1501737812-24171-1-git-send-email-jacob-chen@iotwrt.com (mailing list archive)
State New, archived
Headers show

Commit Message

Jacob Chen Aug. 3, 2017, 5:23 a.m. UTC 
Rockchip RGA is a separate 2D raster graphic acceleration unit. It
accelerates 2D graphics operations, such as point/line drawing, image
scaling, rotation, BitBLT, alpha blending and image blur/sharpness

The drvier is mostly based on s5p-g2d v4l2 m2m driver
And supports various operations from the rendering pipeline.
 - copy
 - fast solid color fill
 - rotation
 - flip
 - alpha blending

The code in rga-hw.c is used to configure regs according to operations
The code in rga-buf.c is used to create private mmu table for RGA.

changes in V7:
- fix some warning reported by "checkpatch --strict"

Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
---
 drivers/media/platform/Kconfig                |   11 +
 drivers/media/platform/Makefile               |    2 +
 drivers/media/platform/rockchip-rga/Makefile  |    3 +
 drivers/media/platform/rockchip-rga/rga-buf.c |  155 ++++
 drivers/media/platform/rockchip-rga/rga-hw.c  |  670 ++++++++++++++++
 drivers/media/platform/rockchip-rga/rga-hw.h  |  437 +++++++++++
 drivers/media/platform/rockchip-rga/rga.c     | 1026 +++++++++++++++++++++++++
 drivers/media/platform/rockchip-rga/rga.h     |  110 +++
 8 files changed, 2414 insertions(+)
 create mode 100644 drivers/media/platform/rockchip-rga/Makefile
 create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
 create mode 100644 drivers/media/platform/rockchip-rga/rga.c
 create mode 100644 drivers/media/platform/rockchip-rga/rga.h

Comments

kernel test robot Aug. 13, 2017, 12:44 a.m. UTC | #1 
Hi Jacob,

[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.13-rc4 next-20170811]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jacob-Chen/rockchip-rga-v4l2-m2m-support/20170803-234713
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: openrisc-allyesconfig (attached as .config)
compiler: or1k-linux-gcc (GCC) 5.4.0
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=openrisc 

All errors (new ones prefixed by >>):

   drivers/media/platform/rockchip-rga/rga.c: In function 'rga_s_ctrl':
>> drivers/media/platform/rockchip-rga/rga.c:159:7: error: 'V4L2_CID_PORTER_DUFF_MODE' undeclared (first use in this function)
     case V4L2_CID_PORTER_DUFF_MODE:
          ^
   drivers/media/platform/rockchip-rga/rga.c:159:7: note: each undeclared identifier is reported only once for each function it appears in
   drivers/media/platform/rockchip-rga/rga.c: In function 'rga_setup_ctrls':
   drivers/media/platform/rockchip-rga/rga.c:190:11: error: 'V4L2_CID_PORTER_DUFF_MODE' undeclared (first use in this function)
              V4L2_CID_PORTER_DUFF_MODE,
              ^
   drivers/media/platform/rockchip-rga/rga.c:191:11: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
              V4L2_PORTER_DUFF_CLEAR, 0,
              ^
   drivers/media/platform/rockchip-rga/rga.c:192:11: error: 'V4L2_PORTER_DUFF_SRC' undeclared (first use in this function)
              V4L2_PORTER_DUFF_SRC);
              ^
   drivers/media/platform/rockchip-rga/rga.c: At top level:
   drivers/media/platform/rockchip-rga/rga.c:742:12: warning: 'rga_enable_clocks' defined but not used [-Wunused-function]
    static int rga_enable_clocks(struct rockchip_rga *rga)
               ^
   drivers/media/platform/rockchip-rga/rga.c:774:13: warning: 'rga_disable_clocks' defined but not used [-Wunused-function]
    static void rga_disable_clocks(struct rockchip_rga *rga)
                ^
--
   drivers/media/platform/rockchip-rga/rga-hw.c: In function 'rga_cmd_set_trans_info':
   drivers/media/platform/rockchip-rga/rga-hw.c:237:17: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
     if (ctx->op == V4L2_PORTER_DUFF_CLEAR) {
                    ^
   drivers/media/platform/rockchip-rga/rga-hw.c:237:17: note: each undeclared identifier is reported only once for each function it appears in
   drivers/media/platform/rockchip-rga/rga-hw.c: In function 'rga_cmd_set_mode':
   drivers/media/platform/rockchip-rga/rga-hw.c:391:7: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_CLEAR:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c:397:7: error: 'V4L2_PORTER_DUFF_DST' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DST:
          ^
>> drivers/media/platform/rockchip-rga/rga-hw.c:398:7: error: 'V4L2_PORTER_DUFF_DSTATOP' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTATOP:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c:399:7: error: 'V4L2_PORTER_DUFF_DSTIN' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTIN:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c:400:7: error: 'V4L2_PORTER_DUFF_DSTOUT' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTOUT:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c:401:7: error: 'V4L2_PORTER_DUFF_DSTOVER' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTOVER:
          ^
>> drivers/media/platform/rockchip-rga/rga-hw.c:402:7: error: 'V4L2_PORTER_DUFF_SRCATOP' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCATOP:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c:403:7: error: 'V4L2_PORTER_DUFF_SRCIN' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCIN:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c:404:7: error: 'V4L2_PORTER_DUFF_SRCOUT' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCOUT:
          ^
>> drivers/media/platform/rockchip-rga/rga-hw.c:405:7: error: 'V4L2_PORTER_DUFF_SRCOVER' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCOVER:
          ^
   drivers/media/platform/rockchip-rga/rga-hw.c: In function 'rga_cmd_set':
   drivers/media/platform/rockchip-rga/rga-hw.c:623:17: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
     if (ctx->op != V4L2_PORTER_DUFF_CLEAR) {
                    ^

vim +/V4L2_CID_PORTER_DUFF_MODE +159 drivers/media/platform/rockchip-rga/rga.c

   150	
   151	static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
   152	{
   153		struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
   154						   ctrl_handler);
   155		unsigned long flags;
   156	
   157		spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
   158		switch (ctrl->id) {
 > 159		case V4L2_CID_PORTER_DUFF_MODE:
   160			ctx->op = ctrl->val;
   161			break;
   162		case V4L2_CID_HFLIP:
   163			ctx->hflip = ctrl->val;
   164			break;
   165		case V4L2_CID_VFLIP:
   166			ctx->vflip = ctrl->val;
   167			break;
   168		case V4L2_CID_ROTATE:
   169			ctx->rotate = ctrl->val;
   170			break;
   171		case V4L2_CID_BG_COLOR:
   172			ctx->fill_color = ctrl->val;
   173			break;
   174		}
   175		spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
   176		return 0;
   177	}
   178	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
kernel test robot Aug. 13, 2017, 1:04 a.m. UTC | #2 
Hi Jacob,

[auto build test ERROR on rockchip/for-next]
[also build test ERROR on v4.13-rc4 next-20170811]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]

url:    https://github.com/0day-ci/linux/commits/Jacob-Chen/rockchip-rga-v4l2-m2m-support/20170803-234713
base:   https://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip.git for-next
config: s390-allmodconfig (attached as .config)
compiler: s390x-linux-gnu-gcc (Debian 6.1.1-9) 6.1.1 20160705
reproduce:
        wget https://raw.githubusercontent.com/01org/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # save the attached .config to linux build tree
        make.cross ARCH=s390 

All errors (new ones prefixed by >>):

   drivers/media/platform/rockchip-rga/rga-hw.c: In function 'rga_cmd_set_trans_info':
   drivers/media/platform/rockchip-rga/rga-hw.c:237:17: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
     if (ctx->op == V4L2_PORTER_DUFF_CLEAR) {
                    ^~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:237:17: note: each undeclared identifier is reported only once for each function it appears in
   drivers/media/platform/rockchip-rga/rga-hw.c: In function 'rga_cmd_set_mode':
   drivers/media/platform/rockchip-rga/rga-hw.c:391:7: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_CLEAR:
          ^~~~~~~~~~~~~~~~~~~~~~
>> drivers/media/platform/rockchip-rga/rga-hw.c:397:7: error: 'V4L2_PORTER_DUFF_DST' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DST:
          ^~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:398:7: error: 'V4L2_PORTER_DUFF_DSTATOP' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTATOP:
          ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:399:7: error: 'V4L2_PORTER_DUFF_DSTIN' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTIN:
          ^~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:400:7: error: 'V4L2_PORTER_DUFF_DSTOUT' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTOUT:
          ^~~~~~~~~~~~~~~~~~~~~~~
>> drivers/media/platform/rockchip-rga/rga-hw.c:401:7: error: 'V4L2_PORTER_DUFF_DSTOVER' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_DSTOVER:
          ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:402:7: error: 'V4L2_PORTER_DUFF_SRCATOP' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCATOP:
          ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:403:7: error: 'V4L2_PORTER_DUFF_SRCIN' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCIN:
          ^~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:404:7: error: 'V4L2_PORTER_DUFF_SRCOUT' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCOUT:
          ^~~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c:405:7: error: 'V4L2_PORTER_DUFF_SRCOVER' undeclared (first use in this function)
     case V4L2_PORTER_DUFF_SRCOVER:
          ^~~~~~~~~~~~~~~~~~~~~~~~
   drivers/media/platform/rockchip-rga/rga-hw.c: In function 'rga_cmd_set':
   drivers/media/platform/rockchip-rga/rga-hw.c:623:17: error: 'V4L2_PORTER_DUFF_CLEAR' undeclared (first use in this function)
     if (ctx->op != V4L2_PORTER_DUFF_CLEAR) {
                    ^~~~~~~~~~~~~~~~~~~~~~

vim +/V4L2_PORTER_DUFF_DST +397 drivers/media/platform/rockchip-rga/rga-hw.c

   168	
   169	static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
   170	{
   171		struct rockchip_rga *rga = ctx->rga;
   172		u32 *dest = rga->cmdbuf_virt;
   173		unsigned int scale_dst_w, scale_dst_h;
   174		unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
   175		union rga_src_info src_info;
   176		union rga_dst_info dst_info;
   177		union rga_src_x_factor x_factor;
   178		union rga_src_y_factor y_factor;
   179		union rga_src_vir_info src_vir_info;
   180		union rga_src_act_info src_act_info;
   181		union rga_dst_vir_info dst_vir_info;
   182		union rga_dst_act_info dst_act_info;
   183	
   184		struct rga_addr_offset *dst_offset;
   185		struct rga_corners_addr_offset offsets;
   186		struct rga_corners_addr_offset src_offsets;
   187	
   188		src_h = ctx->in.crop.height;
   189		src_w = ctx->in.crop.width;
   190		src_x = ctx->in.crop.left;
   191		src_y = ctx->in.crop.top;
   192		dst_h = ctx->out.crop.height;
   193		dst_w = ctx->out.crop.width;
   194		dst_x = ctx->out.crop.left;
   195		dst_y = ctx->out.crop.top;
   196	
   197		src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
   198		dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
   199		x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
   200		y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
   201		src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
   202		src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
   203		dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
   204		dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
   205	
   206		src_info.data.format = ctx->in.fmt->hw_format;
   207		src_info.data.swap = ctx->in.fmt->color_swap;
   208		dst_info.data.format = ctx->out.fmt->hw_format;
   209		dst_info.data.swap = ctx->out.fmt->color_swap;
   210	
   211		if (ctx->in.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
   212			if (ctx->out.fmt->hw_format < RGA_COLOR_FMT_YUV422SP) {
   213				switch (ctx->in.colorspace) {
   214				case V4L2_COLORSPACE_REC709:
   215					src_info.data.csc_mode =
   216						RGA_SRC_CSC_MODE_BT709_R0;
   217					break;
   218				default:
   219					src_info.data.csc_mode =
   220						RGA_SRC_CSC_MODE_BT601_R0;
   221					break;
   222				}
   223			}
   224		}
   225	
   226		if (ctx->out.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
   227			switch (ctx->out.colorspace) {
   228			case V4L2_COLORSPACE_REC709:
   229				dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
   230				break;
   231			default:
   232				dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
   233				break;
   234			}
   235		}
   236	
 > 237		if (ctx->op == V4L2_PORTER_DUFF_CLEAR) {
   238			/*
   239			 * Configure the target color to foreground color.
   240			 */
   241			dest[(RGA_SRC_FG_COLOR - RGA_MODE_BASE_REG) >> 2] =
   242				ctx->fill_color;
   243			dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
   244			dst_act_info.data.act_height = dst_h - 1;
   245			dst_act_info.data.act_width = dst_w - 1;
   246	
   247			offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y,
   248						      dst_w, dst_h);
   249			dst_offset = &offsets.left_top;
   250	
   251			goto write_dst;
   252		}
   253	
   254		if (ctx->vflip)
   255			src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
   256	
   257		if (ctx->hflip)
   258			src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
   259	
   260		switch (ctx->rotate) {
   261		case 90:
   262			src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
   263			break;
   264		case 180:
   265			src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
   266			break;
   267		case 270:
   268			src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
   269			break;
   270		default:
   271			src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
   272			break;
   273		}
   274	
   275		/*
   276		 * Cacluate the up/down scaling mode/factor.
   277		 *
   278		 * RGA used to scale the picture first, and then rotate second,
   279		 * so we need to swap the w/h when rotate degree is 90/270.
   280		 */
   281		if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
   282		    src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
   283			if (rga->version.major == 0 || rga->version.minor == 0) {
   284				if (dst_w == src_h)
   285					src_h -= 8;
   286				if (abs(src_w - dst_h) < 16)
   287					src_w -= 16;
   288			}
   289	
   290			scale_dst_h = dst_w;
   291			scale_dst_w = dst_h;
   292		} else {
   293			scale_dst_w = dst_w;
   294			scale_dst_h = dst_h;
   295		}
   296	
   297		if (src_w == scale_dst_w) {
   298			src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
   299			x_factor.val = 0;
   300		} else if (src_w > scale_dst_w) {
   301			src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
   302			x_factor.data.down_scale_factor =
   303				rga_get_scaling(src_w, scale_dst_w) + 1;
   304		} else {
   305			src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
   306			x_factor.data.up_scale_factor =
   307				rga_get_scaling(src_w - 1, scale_dst_w - 1);
   308		}
   309	
   310		if (src_h == scale_dst_h) {
   311			src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
   312			y_factor.val = 0;
   313		} else if (src_h > scale_dst_h) {
   314			src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
   315			y_factor.data.down_scale_factor =
   316				rga_get_scaling(src_h, scale_dst_h) + 1;
   317		} else {
   318			src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
   319			y_factor.data.up_scale_factor =
   320				rga_get_scaling(src_h - 1, scale_dst_h - 1);
   321		}
   322	
   323		/*
   324		 * Cacluate the framebuffer virtual strides and active size,
   325		 * note that the step of vir_stride / vir_width is 4 byte words
   326		 */
   327		src_vir_info.data.vir_stride = ctx->in.stride >> 2;
   328		src_vir_info.data.vir_width = ctx->in.stride >> 2;
   329	
   330		src_act_info.data.act_height = src_h - 1;
   331		src_act_info.data.act_width = src_w - 1;
   332	
   333		dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
   334		dst_act_info.data.act_height = dst_h - 1;
   335		dst_act_info.data.act_width = dst_w - 1;
   336	
   337		/*
   338		 * Cacluate the source framebuffer base address with offset pixel.
   339		 */
   340		src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
   341						  src_w, src_h);
   342	
   343		/*
   344		 * Configure the dest framebuffer base address with pixel offset.
   345		 */
   346		offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
   347		dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
   348						 src_info.data.mir_mode);
   349	
   350		dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
   351			src_offsets.left_top.y_off;
   352		dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
   353			src_offsets.left_top.u_off;
   354		dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
   355			src_offsets.left_top.v_off;
   356	
   357		dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
   358		dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
   359		dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
   360		dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
   361	
   362		dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
   363	
   364	write_dst:
   365		dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
   366			dst_offset->y_off;
   367		dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
   368			dst_offset->u_off;
   369		dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
   370			dst_offset->v_off;
   371	
   372		dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
   373		dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
   374	
   375		dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
   376	}
   377	
   378	static void rga_cmd_set_mode(struct rga_ctx *ctx)
   379	{
   380		struct rockchip_rga *rga = ctx->rga;
   381		u32 *dest = rga->cmdbuf_virt;
   382		union rga_mode_ctrl mode;
   383		union rga_alpha_ctrl0 alpha_ctrl0;
   384		union rga_alpha_ctrl1 alpha_ctrl1;
   385	
   386		mode.val = 0;
   387		alpha_ctrl0.val = 0;
   388		alpha_ctrl1.val = 0;
   389	
   390		switch (ctx->op) {
   391		case V4L2_PORTER_DUFF_CLEAR:
   392			mode.data.gradient_sat = 1;
   393			mode.data.render = RGA_MODE_RENDER_RECTANGLE_FILL;
   394			mode.data.cf_rop4_pat = RGA_MODE_CF_ROP4_SOLID;
   395			mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
   396			break;
 > 397		case V4L2_PORTER_DUFF_DST:
 > 398		case V4L2_PORTER_DUFF_DSTATOP:
   399		case V4L2_PORTER_DUFF_DSTIN:
   400		case V4L2_PORTER_DUFF_DSTOUT:
 > 401		case V4L2_PORTER_DUFF_DSTOVER:
   402		case V4L2_PORTER_DUFF_SRCATOP:
   403		case V4L2_PORTER_DUFF_SRCIN:
   404		case V4L2_PORTER_DUFF_SRCOUT:
   405		case V4L2_PORTER_DUFF_SRCOVER:
   406			mode.data.gradient_sat = 1;
   407			mode.data.render = RGA_MODE_RENDER_BITBLT;
   408			mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
   409	
   410			alpha_ctrl0.data.rop_en = 1;
   411			alpha_ctrl0.data.rop_mode = RGA_ALPHA_ROP_MODE_3;
   412			alpha_ctrl0.data.rop_select = RGA_ALPHA_SELECT_ALPHA;
   413	
   414			alpha_ctrl1.data.dst_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
   415			alpha_ctrl1.data.src_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
   416			alpha_ctrl1.data.dst_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
   417			alpha_ctrl1.data.src_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
   418			break;
   419		default:
   420			mode.data.gradient_sat = 1;
   421			mode.data.render = RGA_MODE_RENDER_BITBLT;
   422			mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
   423			break;
   424		}
   425	
   426		switch (ctx->op) {
   427		case V4L2_PORTER_DUFF_DST:
   428			/* A=Dst.a */
   429			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   430	
   431			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   432			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   433			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
   434	
   435			/* C=Dst.c */
   436			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
   437	
   438			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   439			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   440			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   441			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
   442			break;
   443		case V4L2_PORTER_DUFF_DSTATOP:
   444			/* A=Src.a */
   445			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   446			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   447			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
   448	
   449			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   450	
   451			/* C=Src.a*Dst.c+Src.c*(1.0-Dst.a) */
   452			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   453			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   454			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   455			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   456	
   457			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   458			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   459			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   460			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
   461			break;
   462		case V4L2_PORTER_DUFF_DSTIN:
   463			/* A=Dst.a*Src.a */
   464			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   465			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   466			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   467	
   468			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   469			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   470			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
   471	
   472			/* C=Dst.c*Src.a */
   473			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   474			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   475			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   476			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
   477	
   478			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   479			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   480			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   481			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
   482			break;
   483		case V4L2_PORTER_DUFF_DSTOUT:
   484			/* A=Dst.a*(1.0-Src.a) */
   485			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   486			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   487			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   488	
   489			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   490			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   491			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   492	
   493			/* C=Dst.c*(1.0-Src.a) */
   494			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   495			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   496			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   497			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
   498	
   499			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   500			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   501			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   502			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   503			break;
   504		case V4L2_PORTER_DUFF_DSTOVER:
   505			/* A=Src.a+Dst.a*(1.0-Src.a) */
   506			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   507			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   508			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
   509	
   510			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   511			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   512			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   513	
   514			/* C=Dst.c+Src.c*(1.0-Dst.a) */
   515			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   516			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   517			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   518			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   519	
   520			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   521			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   522			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   523			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
   524			break;
   525		case V4L2_PORTER_DUFF_SRCATOP:
   526			/* A=Dst.a */
   527			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   528	
   529			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   530			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   531			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
   532	
   533			/* C=Dst.a*Src.c+Dst.c*(1.0-Src.a) */
   534			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   535			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   536			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   537			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
   538	
   539			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   540			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   541			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   542			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   543			break;
   544		case V4L2_PORTER_DUFF_SRCIN:
   545			/* A=Src.a*Dst.a */
   546			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   547			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   548			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   549	
   550			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   551			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   552			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
   553	
   554			/* C=Src.c*Dst.a */
   555			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   556			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   557			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   558			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
   559	
   560			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   561			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   562			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   563			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
   564			break;
   565		case V4L2_PORTER_DUFF_SRCOUT:
   566			/* A=Src.a*(1.0-Dst.a) */
   567			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   568			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   569			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   570	
   571			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   572			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   573			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
   574	
   575			/* C=Src.c*(1.0-Dst.a) */
   576			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   577			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   578			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   579			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   580	
   581			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   582			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   583			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   584			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
   585			break;
   586		case V4L2_PORTER_DUFF_SRCOVER:
   587			/* A=Src.a+Dst.a*(1.0-Src.a) */
   588			alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
   589			alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   590			alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
   591	
   592			alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
   593			alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
   594			alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   595	
   596			/* C=Src.c+Dst.c*(1.0-Src.a) */
   597			alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   598			alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
   599			alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   600			alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ONE;
   601	
   602			alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
   603			alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
   604			alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
   605			alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
   606			break;
   607		default:
   608			break;
   609		}
   610	
   611		dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
   612		dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
   613	
   614		dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
   615	}
   616	

---
0-DAY kernel test infrastructure                Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all                   Intel Corporation
Hans Verkuil Aug. 21, 2017, 2:16 p.m. UTC | #3 
Hi Jacob,

On 08/03/2017 07:23 AM, Jacob Chen wrote:
> Rockchip RGA is a separate 2D raster graphic acceleration unit. It
> accelerates 2D graphics operations, such as point/line drawing, image
> scaling, rotation, BitBLT, alpha blending and image blur/sharpness
> 
> The drvier is mostly based on s5p-g2d v4l2 m2m driver
> And supports various operations from the rendering pipeline.
>  - copy
>  - fast solid color fill
>  - rotation
>  - flip
>  - alpha blending
> 
> The code in rga-hw.c is used to configure regs according to operations
> The code in rga-buf.c is used to create private mmu table for RGA.
> 
> changes in V7:
> - fix some warning reported by "checkpatch --strict"
> 
> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>

Can you post the v4l2-compliance output? I gather that there is at least one
colorspace-related error that appears to be a v4l2-compliance bug, so I'd
like to see the exact error it gives. I'll see if I can fix it so this driver
has a clean compliance output.

I apologize that this driver probably won't make 4.14. Too much to review...

I hope to do the v7 review within a week.

Regards,

	Hans
Hans Verkuil Aug. 25, 2017, 12:09 p.m. UTC | #4 
Hi Jacob,

As promised, some more (small) review comments below.

On 03/08/17 07:23, Jacob Chen wrote:
> Rockchip RGA is a separate 2D raster graphic acceleration unit. It
> accelerates 2D graphics operations, such as point/line drawing, image
> scaling, rotation, BitBLT, alpha blending and image blur/sharpness
> 
> The drvier is mostly based on s5p-g2d v4l2 m2m driver

driver

> And supports various operations from the rendering pipeline.
>  - copy
>  - fast solid color fill
>  - rotation
>  - flip
>  - alpha blending
> 
> The code in rga-hw.c is used to configure regs according to operations
> The code in rga-buf.c is used to create private mmu table for RGA.
> 
> changes in V7:
> - fix some warning reported by "checkpatch --strict"
> 
> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
> ---
>  drivers/media/platform/Kconfig                |   11 +
>  drivers/media/platform/Makefile               |    2 +
>  drivers/media/platform/rockchip-rga/Makefile  |    3 +
>  drivers/media/platform/rockchip-rga/rga-buf.c |  155 ++++
>  drivers/media/platform/rockchip-rga/rga-hw.c  |  670 ++++++++++++++++
>  drivers/media/platform/rockchip-rga/rga-hw.h  |  437 +++++++++++
>  drivers/media/platform/rockchip-rga/rga.c     | 1026 +++++++++++++++++++++++++
>  drivers/media/platform/rockchip-rga/rga.h     |  110 +++
>  8 files changed, 2414 insertions(+)
>  create mode 100644 drivers/media/platform/rockchip-rga/Makefile
>  create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
>  create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
>  create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
>  create mode 100644 drivers/media/platform/rockchip-rga/rga.c
>  create mode 100644 drivers/media/platform/rockchip-rga/rga.h
> 
> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
> index 041cb80a..d0d1a21 100644
> --- a/drivers/media/platform/Kconfig
> +++ b/drivers/media/platform/Kconfig
> @@ -427,6 +427,17 @@ config VIDEO_RENESAS_VSP1
>  	  To compile this driver as a module, choose M here: the module
>  	  will be called vsp1.
>  
> +config VIDEO_ROCKCHIP_RGA
> +	tristate "Rockchip Raster 2d Grapphic Acceleration Unit"
> +	depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
> +	depends on ARCH_ROCKCHIP || COMPILE_TEST
> +	select VIDEOBUF2_DMA_SG
> +	select V4L2_MEM2MEM_DEV
> +	default n
> +	---help---
> +	  This is a v4l2 driver for Rockchip SOC RGA2
> +	  2d graphics accelerator.
> +
>  config VIDEO_TI_VPE
>  	tristate "TI VPE (Video Processing Engine) driver"
>  	depends on VIDEO_DEV && VIDEO_V4L2
> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
> index 63303d6..baf83060 100644
> --- a/drivers/media/platform/Makefile
> +++ b/drivers/media/platform/Makefile
> @@ -57,6 +57,8 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1)	+= rcar_fdp1.o
>  obj-$(CONFIG_VIDEO_RENESAS_JPU) 	+= rcar_jpu.o
>  obj-$(CONFIG_VIDEO_RENESAS_VSP1)	+= vsp1/
>  
> +obj-$(CONFIG_VIDEO_ROCKCHIP_RGA)	+= rockchip-rga/
> +
>  obj-y	+= omap/
>  
>  obj-$(CONFIG_VIDEO_AM437X_VPFE)		+= am437x/
> diff --git a/drivers/media/platform/rockchip-rga/Makefile b/drivers/media/platform/rockchip-rga/Makefile
> new file mode 100644
> index 0000000..92fe254
> --- /dev/null
> +++ b/drivers/media/platform/rockchip-rga/Makefile
> @@ -0,0 +1,3 @@
> +rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
> +
> +obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
> diff --git a/drivers/media/platform/rockchip-rga/rga-buf.c b/drivers/media/platform/rockchip-rga/rga-buf.c
> new file mode 100644
> index 0000000..6a9fd2c
> --- /dev/null
> +++ b/drivers/media/platform/rockchip-rga/rga-buf.c
> @@ -0,0 +1,155 @@
> +/*
> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/pm_runtime.h>
> +
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-mem2mem.h>
> +#include <media/videobuf2-dma-sg.h>
> +#include <media/videobuf2-v4l2.h>
> +
> +#include "rga-hw.h"
> +#include "rga.h"
> +
> +static int
> +rga_queue_setup(struct vb2_queue *vq,
> +		unsigned int *nbuffers, unsigned int *nplanes,
> +		unsigned int sizes[], struct device *alloc_devs[])
> +{
> +	struct rga_ctx *ctx = vb2_get_drv_priv(vq);
> +	struct rga_frame *f = rga_get_frame(ctx, vq->type);
> +
> +	if (IS_ERR(f))
> +		return PTR_ERR(f);
> +
> +	if (*nplanes)
> +		return sizes[0] < f->size ? -EINVAL : 0;
> +
> +	sizes[0] = f->size;
> +	*nplanes = 1;
> +
> +	return 0;
> +}
> +
> +static int rga_buf_prepare(struct vb2_buffer *vb)
> +{
> +	struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
> +	struct rga_frame *f = rga_get_frame(ctx, vb->vb2_queue->type);
> +
> +	if (IS_ERR(f))
> +		return PTR_ERR(f);
> +
> +	vb2_set_plane_payload(vb, 0, f->size);
> +
> +	return 0;
> +}
> +
> +static void rga_buf_queue(struct vb2_buffer *vb)
> +{
> +	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
> +	struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
> +
> +	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
> +}
> +
> +static int rga_buf_start_streaming(struct vb2_queue *q, unsigned int count)
> +{
> +	struct rga_ctx *ctx = vb2_get_drv_priv(q);
> +	struct rockchip_rga *rga = ctx->rga;
> +	int ret, i;
> +
> +	ret = pm_runtime_get_sync(rga->dev);
> +
> +	if (ret < 0) {
> +		for (i = 0; i < q->num_buffers; ++i) {
> +			if (q->bufs[i]->state == VB2_BUF_STATE_ACTIVE) {
> +				v4l2_m2m_buf_done(to_vb2_v4l2_buffer(q->bufs[i]),
> +						VB2_BUF_STATE_QUEUED);
> +			}
> +		}
> +
> +		return ret;
> +	}
> +
> +	return 0;
> +}
> +
> +static void rga_buf_stop_streaming(struct vb2_queue *q)
> +{
> +	struct rga_ctx *ctx = vb2_get_drv_priv(q);
> +	struct rockchip_rga *rga = ctx->rga;
> +	struct vb2_v4l2_buffer *vbuf;
> +
> +	for (;;) {
> +		if (V4L2_TYPE_IS_OUTPUT(q->type))
> +			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> +		else
> +			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> +		if (!vbuf)
> +			break;
> +		v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
> +	}
> +
> +	pm_runtime_put(rga->dev);
> +}
> +
> +const struct vb2_ops rga_qops = {
> +	.queue_setup = rga_queue_setup,
> +	.buf_prepare = rga_buf_prepare,
> +	.buf_queue = rga_buf_queue,
> +	.wait_prepare = vb2_ops_wait_prepare,
> +	.wait_finish = vb2_ops_wait_finish,
> +	.start_streaming = rga_buf_start_streaming,
> +	.stop_streaming = rga_buf_stop_streaming,
> +};
> +
> +/* RGA MMU is a 1-Level MMU, so it can't be used through the IOMMU API.
> + * We use it more like a scatter-gather list.
> + */
> +void rga_buf_map(struct vb2_buffer *vb)
> +{
> +	struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
> +	struct rockchip_rga *rga = ctx->rga;
> +	struct sg_table *sgt;
> +	struct scatterlist *sgl;
> +	unsigned int *pages;
> +	unsigned int address, len, i, p;
> +	unsigned int mapped_size = 0;
> +
> +	if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
> +		pages = rga->src_mmu_pages;
> +	else
> +		pages = rga->dst_mmu_pages;
> +
> +	/* Create local MMU table for RGA */
> +	sgt = vb2_plane_cookie(vb, 0);
> +
> +	for_each_sg(sgt->sgl, sgl, sgt->nents, i) {
> +		len = sg_dma_len(sgl) >> PAGE_SHIFT;
> +		address = sg_phys(sgl);
> +
> +		for (p = 0; p < len; p++) {
> +			dma_addr_t phys = address + (p << PAGE_SHIFT);
> +
> +			pages[mapped_size + p] = phys;
> +		}
> +
> +		mapped_size += len;
> +	}
> +
> +	/* sync local MMU table for RGA */
> +	dma_sync_single_for_device(rga->dev, virt_to_phys(pages),
> +				   8 * PAGE_SIZE, DMA_BIDIRECTIONAL);
> +}
> diff --git a/drivers/media/platform/rockchip-rga/rga-hw.c b/drivers/media/platform/rockchip-rga/rga-hw.c
> new file mode 100644
> index 0000000..5b7ee58
> --- /dev/null
> +++ b/drivers/media/platform/rockchip-rga/rga-hw.c
> @@ -0,0 +1,670 @@
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/pm_runtime.h>
> +
> +#include "rga-hw.h"
> +#include "rga.h"
> +
> +enum e_rga_start_pos {
> +	LT = 0,
> +	LB = 1,
> +	RT = 2,
> +	RB = 3,
> +};
> +
> +struct rga_addr_offset {
> +	unsigned int y_off;
> +	unsigned int u_off;
> +	unsigned int v_off;
> +};
> +
> +struct rga_corners_addr_offset {
> +	struct rga_addr_offset left_top;
> +	struct rga_addr_offset right_top;
> +	struct rga_addr_offset left_bottom;
> +	struct rga_addr_offset right_bottom;
> +};
> +
> +static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)
> +{
> +	/*
> +	 * The rga hw scaling factor is a normalized inverse of the
> +	 * scaling factor.
> +	 * For example: When source width is 100 and destination width is 200
> +	 * (scaling of 2x), then the hw factor is NC * 100 / 200.
> +	 * The normalization factor (NC) is 2^16 = 0x10000.
> +	 */
> +
> +	return (src > dst) ? ((dst << 16) / src) : ((src << 16) / dst);
> +}
> +
> +static struct rga_corners_addr_offset
> +rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,
> +		    unsigned int w, unsigned int h)
> +{
> +	struct rga_corners_addr_offset offsets;
> +	struct rga_addr_offset *lt, *lb, *rt, *rb;
> +	unsigned int x_div = 0,
> +		     y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;
> +
> +	lt = &offsets.left_top;
> +	lb = &offsets.left_bottom;
> +	rt = &offsets.right_top;
> +	rb = &offsets.right_bottom;
> +
> +	x_div = frm->fmt->x_div;
> +	y_div = frm->fmt->y_div;
> +	uv_factor = frm->fmt->uv_factor;
> +	uv_stride = frm->stride / x_div;
> +	pixel_width = frm->stride / frm->width;
> +
> +	lt->y_off = y * frm->stride + x * pixel_width;
> +	lt->u_off =
> +		frm->width * frm->height + (y / y_div) * uv_stride + x / x_div;
> +	lt->v_off = lt->u_off + frm->width * frm->height / uv_factor;
> +
> +	lb->y_off = lt->y_off + (h - 1) * frm->stride;
> +	lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride;
> +	lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride;
> +
> +	rt->y_off = lt->y_off + (w - 1) * pixel_width;
> +	rt->u_off = lt->u_off + w / x_div - 1;
> +	rt->v_off = lt->v_off + w / x_div - 1;
> +
> +	rb->y_off = lb->y_off + (w - 1) * pixel_width;
> +	rb->u_off = lb->u_off + w / x_div - 1;
> +	rb->v_off = lb->v_off + w / x_div - 1;
> +
> +	return offsets;
> +}
> +
> +static struct rga_addr_offset *rga_lookup_draw_pos(struct
> +		rga_corners_addr_offset
> +		* offsets, u32 rotate_mode,
> +		u32 mirr_mode)
> +{
> +	static enum e_rga_start_pos rot_mir_point_matrix[4][4] = {
> +		{
> +			LT, RT, LB, RB,
> +		},
> +		{
> +			RT, LT, RB, LB,
> +		},
> +		{
> +			RB, LB, RT, LT,
> +		},
> +		{
> +			LB, RB, LT, RT,
> +		},
> +	};
> +
> +	if (!offsets)
> +		return NULL;
> +
> +	switch (rot_mir_point_matrix[rotate_mode][mirr_mode]) {
> +	case LT:
> +		return &offsets->left_top;
> +	case LB:
> +		return &offsets->left_bottom;
> +	case RT:
> +		return &offsets->right_top;
> +	case RB:
> +		return &offsets->right_bottom;
> +	}
> +
> +	return NULL;
> +}
> +
> +static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +	u32 *dest = rga->cmdbuf_virt;
> +	unsigned int reg;
> +
> +	reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;
> +	dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
> +
> +	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
> +	dest[reg >> 2] |= 0x7;
> +}
> +
> +static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +	u32 *dest = rga->cmdbuf_virt;
> +	unsigned int reg;
> +
> +	reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;
> +	dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
> +
> +	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
> +	dest[reg >> 2] |= 0x7 << 4;
> +}
> +
> +static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +	u32 *dest = rga->cmdbuf_virt;
> +	unsigned int reg;
> +
> +	reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;
> +	dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
> +
> +	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
> +	dest[reg >> 2] |= 0x7 << 8;
> +}
> +
> +static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +	u32 *dest = rga->cmdbuf_virt;
> +	unsigned int scale_dst_w, scale_dst_h;
> +	unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
> +	union rga_src_info src_info;
> +	union rga_dst_info dst_info;
> +	union rga_src_x_factor x_factor;
> +	union rga_src_y_factor y_factor;
> +	union rga_src_vir_info src_vir_info;
> +	union rga_src_act_info src_act_info;
> +	union rga_dst_vir_info dst_vir_info;
> +	union rga_dst_act_info dst_act_info;
> +
> +	struct rga_addr_offset *dst_offset;
> +	struct rga_corners_addr_offset offsets;
> +	struct rga_corners_addr_offset src_offsets;
> +
> +	src_h = ctx->in.crop.height;
> +	src_w = ctx->in.crop.width;
> +	src_x = ctx->in.crop.left;
> +	src_y = ctx->in.crop.top;
> +	dst_h = ctx->out.crop.height;
> +	dst_w = ctx->out.crop.width;
> +	dst_x = ctx->out.crop.left;
> +	dst_y = ctx->out.crop.top;
> +
> +	src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
> +	dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
> +	x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
> +	y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
> +	src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
> +	src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
> +	dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
> +	dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
> +
> +	src_info.data.format = ctx->in.fmt->hw_format;
> +	src_info.data.swap = ctx->in.fmt->color_swap;
> +	dst_info.data.format = ctx->out.fmt->hw_format;
> +	dst_info.data.swap = ctx->out.fmt->color_swap;
> +
> +	if (ctx->in.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
> +		if (ctx->out.fmt->hw_format < RGA_COLOR_FMT_YUV422SP) {
> +			switch (ctx->in.colorspace) {
> +			case V4L2_COLORSPACE_REC709:
> +				src_info.data.csc_mode =
> +					RGA_SRC_CSC_MODE_BT709_R0;
> +				break;
> +			default:
> +				src_info.data.csc_mode =
> +					RGA_SRC_CSC_MODE_BT601_R0;
> +				break;
> +			}
> +		}
> +	}
> +
> +	if (ctx->out.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
> +		switch (ctx->out.colorspace) {
> +		case V4L2_COLORSPACE_REC709:
> +			dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
> +			break;
> +		default:
> +			dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
> +			break;
> +		}
> +	}
> +
> +	if (ctx->op == V4L2_PORTER_DUFF_CLEAR) {
> +		/*
> +		 * Configure the target color to foreground color.
> +		 */
> +		dest[(RGA_SRC_FG_COLOR - RGA_MODE_BASE_REG) >> 2] =
> +			ctx->fill_color;
> +		dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
> +		dst_act_info.data.act_height = dst_h - 1;
> +		dst_act_info.data.act_width = dst_w - 1;
> +
> +		offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y,
> +					      dst_w, dst_h);
> +		dst_offset = &offsets.left_top;
> +
> +		goto write_dst;
> +	}
> +
> +	if (ctx->vflip)
> +		src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
> +
> +	if (ctx->hflip)
> +		src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
> +
> +	switch (ctx->rotate) {
> +	case 90:
> +		src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
> +		break;
> +	case 180:
> +		src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
> +		break;
> +	case 270:
> +		src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
> +		break;
> +	default:
> +		src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
> +		break;
> +	}
> +
> +	/*
> +	 * Cacluate the up/down scaling mode/factor.
> +	 *
> +	 * RGA used to scale the picture first, and then rotate second,
> +	 * so we need to swap the w/h when rotate degree is 90/270.
> +	 */
> +	if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
> +	    src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
> +		if (rga->version.major == 0 || rga->version.minor == 0) {
> +			if (dst_w == src_h)
> +				src_h -= 8;
> +			if (abs(src_w - dst_h) < 16)
> +				src_w -= 16;
> +		}
> +
> +		scale_dst_h = dst_w;
> +		scale_dst_w = dst_h;
> +	} else {
> +		scale_dst_w = dst_w;
> +		scale_dst_h = dst_h;
> +	}
> +
> +	if (src_w == scale_dst_w) {
> +		src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
> +		x_factor.val = 0;
> +	} else if (src_w > scale_dst_w) {
> +		src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
> +		x_factor.data.down_scale_factor =
> +			rga_get_scaling(src_w, scale_dst_w) + 1;
> +	} else {
> +		src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
> +		x_factor.data.up_scale_factor =
> +			rga_get_scaling(src_w - 1, scale_dst_w - 1);
> +	}
> +
> +	if (src_h == scale_dst_h) {
> +		src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
> +		y_factor.val = 0;
> +	} else if (src_h > scale_dst_h) {
> +		src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
> +		y_factor.data.down_scale_factor =
> +			rga_get_scaling(src_h, scale_dst_h) + 1;
> +	} else {
> +		src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
> +		y_factor.data.up_scale_factor =
> +			rga_get_scaling(src_h - 1, scale_dst_h - 1);
> +	}
> +
> +	/*
> +	 * Cacluate the framebuffer virtual strides and active size,
> +	 * note that the step of vir_stride / vir_width is 4 byte words
> +	 */
> +	src_vir_info.data.vir_stride = ctx->in.stride >> 2;
> +	src_vir_info.data.vir_width = ctx->in.stride >> 2;
> +
> +	src_act_info.data.act_height = src_h - 1;
> +	src_act_info.data.act_width = src_w - 1;
> +
> +	dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
> +	dst_act_info.data.act_height = dst_h - 1;
> +	dst_act_info.data.act_width = dst_w - 1;
> +
> +	/*
> +	 * Cacluate the source framebuffer base address with offset pixel.
> +	 */
> +	src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
> +					  src_w, src_h);
> +
> +	/*
> +	 * Configure the dest framebuffer base address with pixel offset.
> +	 */
> +	offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
> +	dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
> +					 src_info.data.mir_mode);
> +
> +	dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
> +		src_offsets.left_top.y_off;
> +	dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
> +		src_offsets.left_top.u_off;
> +	dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
> +		src_offsets.left_top.v_off;
> +
> +	dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
> +	dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
> +	dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
> +	dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
> +
> +	dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
> +
> +write_dst:
> +	dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
> +		dst_offset->y_off;
> +	dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
> +		dst_offset->u_off;
> +	dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
> +		dst_offset->v_off;
> +
> +	dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
> +	dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
> +
> +	dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
> +}
> +
> +static void rga_cmd_set_mode(struct rga_ctx *ctx)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +	u32 *dest = rga->cmdbuf_virt;
> +	union rga_mode_ctrl mode;
> +	union rga_alpha_ctrl0 alpha_ctrl0;
> +	union rga_alpha_ctrl1 alpha_ctrl1;
> +
> +	mode.val = 0;
> +	alpha_ctrl0.val = 0;
> +	alpha_ctrl1.val = 0;
> +
> +	switch (ctx->op) {
> +	case V4L2_PORTER_DUFF_CLEAR:
> +		mode.data.gradient_sat = 1;
> +		mode.data.render = RGA_MODE_RENDER_RECTANGLE_FILL;
> +		mode.data.cf_rop4_pat = RGA_MODE_CF_ROP4_SOLID;
> +		mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
> +		break;
> +	case V4L2_PORTER_DUFF_DST:
> +	case V4L2_PORTER_DUFF_DSTATOP:
> +	case V4L2_PORTER_DUFF_DSTIN:
> +	case V4L2_PORTER_DUFF_DSTOUT:
> +	case V4L2_PORTER_DUFF_DSTOVER:
> +	case V4L2_PORTER_DUFF_SRCATOP:
> +	case V4L2_PORTER_DUFF_SRCIN:
> +	case V4L2_PORTER_DUFF_SRCOUT:
> +	case V4L2_PORTER_DUFF_SRCOVER:
> +		mode.data.gradient_sat = 1;
> +		mode.data.render = RGA_MODE_RENDER_BITBLT;
> +		mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
> +
> +		alpha_ctrl0.data.rop_en = 1;
> +		alpha_ctrl0.data.rop_mode = RGA_ALPHA_ROP_MODE_3;
> +		alpha_ctrl0.data.rop_select = RGA_ALPHA_SELECT_ALPHA;
> +
> +		alpha_ctrl1.data.dst_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
> +		alpha_ctrl1.data.src_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
> +		alpha_ctrl1.data.src_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
> +		break;
> +	default:
> +		mode.data.gradient_sat = 1;
> +		mode.data.render = RGA_MODE_RENDER_BITBLT;
> +		mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
> +		break;
> +	}
> +
> +	switch (ctx->op) {
> +	case V4L2_PORTER_DUFF_DST:
> +		/* A=Dst.a */
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
> +
> +		/* C=Dst.c */
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
> +		break;
> +	case V4L2_PORTER_DUFF_DSTATOP:
> +		/* A=Src.a */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
> +
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		/* C=Src.a*Dst.c+Src.c*(1.0-Dst.a) */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
> +		break;
> +	case V4L2_PORTER_DUFF_DSTIN:
> +		/* A=Dst.a*Src.a */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
> +
> +		/* C=Dst.c*Src.a */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
> +		break;
> +	case V4L2_PORTER_DUFF_DSTOUT:
> +		/* A=Dst.a*(1.0-Src.a) */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		/* C=Dst.c*(1.0-Src.a) */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +		break;
> +	case V4L2_PORTER_DUFF_DSTOVER:
> +		/* A=Src.a+Dst.a*(1.0-Src.a) */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		/* C=Dst.c+Src.c*(1.0-Dst.a) */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
> +		break;
> +	case V4L2_PORTER_DUFF_SRCATOP:
> +		/* A=Dst.a */
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
> +
> +		/* C=Dst.a*Src.c+Dst.c*(1.0-Src.a) */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +		break;
> +	case V4L2_PORTER_DUFF_SRCIN:
> +		/* A=Src.a*Dst.a */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
> +
> +		/* C=Src.c*Dst.a */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
> +		break;
> +	case V4L2_PORTER_DUFF_SRCOUT:
> +		/* A=Src.a*(1.0-Dst.a) */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
> +
> +		/* C=Src.c*(1.0-Dst.a) */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
> +		break;
> +	case V4L2_PORTER_DUFF_SRCOVER:
> +		/* A=Src.a+Dst.a*(1.0-Src.a) */
> +		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
> +
> +		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +
> +		/* C=Src.c+Dst.c*(1.0-Src.a) */
> +		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ONE;
> +
> +		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
> +		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
> +		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
> +		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
> +		break;
> +	default:
> +		break;
> +	}
> +
> +	dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
> +	dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
> +
> +	dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
> +}
> +
> +void rga_cmd_set(struct rga_ctx *ctx)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +
> +	memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
> +
> +	if (ctx->op != V4L2_PORTER_DUFF_CLEAR) {
> +		rga_cmd_set_src_addr(ctx, rga->src_mmu_pages);
> +		/*
> +		 * Due to hardware bug,
> +		 * src1 mmu also should be configured when using alpha blending.
> +		 */
> +		rga_cmd_set_src1_addr(ctx, rga->dst_mmu_pages);
> +	}
> +	rga_cmd_set_dst_addr(ctx, rga->dst_mmu_pages);
> +	rga_cmd_set_mode(ctx);
> +
> +	rga_cmd_set_trans_info(ctx);
> +
> +	rga_write(rga, RGA_CMD_BASE, rga->cmdbuf_phy);
> +}
> +
> +void rga_write(struct rockchip_rga *rga, u32 reg, u32 value)
> +{
> +	writel(value, rga->regs + reg);
> +}
> +
> +u32 rga_read(struct rockchip_rga *rga, u32 reg)
> +{
> +	return readl(rga->regs + reg);
> +}
> +
> +void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
> +{
> +	u32 temp = rga_read(rga, reg) & ~(mask);
> +
> +	temp |= val & mask;
> +	rga_write(rga, reg, temp);
> +}
> +
> +void rga_start(struct rockchip_rga *rga)
> +{
> +	/* sync CMD buf for RGA */
> +	dma_sync_single_for_device(rga->dev, rga->cmdbuf_phy,
> +				   PAGE_SIZE, DMA_BIDIRECTIONAL);
> +
> +	rga_write(rga, RGA_SYS_CTRL, 0x00);
> +
> +	rga_write(rga, RGA_SYS_CTRL, 0x22);
> +
> +	rga_write(rga, RGA_INT, 0x600);
> +
> +	rga_write(rga, RGA_CMD_CTRL, 0x1);
> +}
> diff --git a/drivers/media/platform/rockchip-rga/rga-hw.h b/drivers/media/platform/rockchip-rga/rga-hw.h
> new file mode 100644
> index 0000000..a8b6353
> --- /dev/null
> +++ b/drivers/media/platform/rockchip-rga/rga-hw.h
> @@ -0,0 +1,437 @@
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __RGA_HW_H__
> +#define __RGA_HW_H__
> +
> +#define RGA_CMDBUF_SIZE 0x20
> +
> +/* Hardware limits */
> +#define MAX_WIDTH 8192
> +#define MAX_HEIGHT 8192
> +
> +#define MIN_WIDTH 34
> +#define MIN_HEIGHT 34
> +
> +#define DEFAULT_WIDTH 100
> +#define DEFAULT_HEIGHT 100
> +
> +#define RGA_TIMEOUT 500
> +
> +/* Registers address */
> +#define RGA_SYS_CTRL 0x0000
> +#define RGA_CMD_CTRL 0x0004
> +#define RGA_CMD_BASE 0x0008
> +#define RGA_INT 0x0010
> +#define RGA_MMU_CTRL0 0x0014
> +#define RGA_VERSION_INFO 0x0028
> +
> +#define RGA_MODE_BASE_REG 0x0100
> +#define RGA_MODE_MAX_REG 0x017C
> +
> +#define RGA_MODE_CTRL 0x0100
> +#define RGA_SRC_INFO 0x0104
> +#define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
> +#define RGA_SRC_CB_BASE_ADDR 0x010c
> +#define RGA_SRC_CR_BASE_ADDR 0x0110
> +#define RGA_SRC1_RGB_BASE_ADDR 0x0114
> +#define RGA_SRC_VIR_INFO 0x0118
> +#define RGA_SRC_ACT_INFO 0x011c
> +#define RGA_SRC_X_FACTOR 0x0120
> +#define RGA_SRC_Y_FACTOR 0x0124
> +#define RGA_SRC_BG_COLOR 0x0128
> +#define RGA_SRC_FG_COLOR 0x012c
> +#define RGA_SRC_TR_COLOR0 0x0130
> +#define RGA_SRC_TR_COLOR1 0x0134
> +
> +#define RGA_DST_INFO 0x0138
> +#define RGA_DST_Y_RGB_BASE_ADDR 0x013c
> +#define RGA_DST_CB_BASE_ADDR 0x0140
> +#define RGA_DST_CR_BASE_ADDR 0x0144
> +#define RGA_DST_VIR_INFO 0x0148
> +#define RGA_DST_ACT_INFO 0x014c
> +
> +#define RGA_ALPHA_CTRL0 0x0150
> +#define RGA_ALPHA_CTRL1 0x0154
> +#define RGA_FADING_CTRL 0x0158
> +#define RGA_PAT_CON 0x015c
> +#define RGA_ROP_CON0 0x0160
> +#define RGA_ROP_CON1 0x0164
> +#define RGA_MASK_BASE 0x0168
> +
> +#define RGA_MMU_CTRL1 0x016C
> +#define RGA_MMU_SRC_BASE 0x0170
> +#define RGA_MMU_SRC1_BASE 0x0174
> +#define RGA_MMU_DST_BASE 0x0178
> +
> +/* Registers value */
> +#define RGA_MODE_RENDER_BITBLT 0
> +#define RGA_MODE_RENDER_COLOR_PALETTE 1
> +#define RGA_MODE_RENDER_RECTANGLE_FILL 2
> +#define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
> +
> +#define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
> +#define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
> +
> +#define RGA_MODE_CF_ROP4_SOLID 0
> +#define RGA_MODE_CF_ROP4_PATTERN 1
> +
> +#define RGA_COLOR_FMT_ABGR8888 0
> +#define RGA_COLOR_FMT_XBGR8888 1
> +#define RGA_COLOR_FMT_BGR888 2
> +#define RGA_COLOR_FMT_BGR565 4
> +#define RGA_COLOR_FMT_ABGR1555 5
> +#define RGA_COLOR_FMT_ABGR4444 6
> +#define RGA_COLOR_FMT_YUV422SP 8
> +#define RGA_COLOR_FMT_YUV422P 9
> +#define RGA_COLOR_FMT_YUV420SP 10
> +#define RGA_COLOR_FMT_YUV420P 11
> +/* SRC_COLOR Palette */
> +#define RGA_COLOR_FMT_CP_1BPP 12
> +#define RGA_COLOR_FMT_CP_2BPP 13
> +#define RGA_COLOR_FMT_CP_4BPP 14
> +#define RGA_COLOR_FMT_CP_8BPP 15
> +#define RGA_COLOR_FMT_MASK 15
> +
> +#define RGA_COLOR_NONE_SWAP 0
> +#define RGA_COLOR_RB_SWAP 1
> +#define RGA_COLOR_ALPHA_SWAP 2
> +#define RGA_COLOR_UV_SWAP 4
> +
> +#define RGA_SRC_CSC_MODE_BYPASS 0
> +#define RGA_SRC_CSC_MODE_BT601_R0 1
> +#define RGA_SRC_CSC_MODE_BT601_R1 2
> +#define RGA_SRC_CSC_MODE_BT709_R0 3
> +#define RGA_SRC_CSC_MODE_BT709_R1 4
> +
> +#define RGA_SRC_ROT_MODE_0_DEGREE 0
> +#define RGA_SRC_ROT_MODE_90_DEGREE 1
> +#define RGA_SRC_ROT_MODE_180_DEGREE 2
> +#define RGA_SRC_ROT_MODE_270_DEGREE 3
> +
> +#define RGA_SRC_MIRR_MODE_NO 0
> +#define RGA_SRC_MIRR_MODE_X 1
> +#define RGA_SRC_MIRR_MODE_Y 2
> +#define RGA_SRC_MIRR_MODE_X_Y 3
> +
> +#define RGA_SRC_HSCL_MODE_NO 0
> +#define RGA_SRC_HSCL_MODE_DOWN 1
> +#define RGA_SRC_HSCL_MODE_UP 2
> +
> +#define RGA_SRC_VSCL_MODE_NO 0
> +#define RGA_SRC_VSCL_MODE_DOWN 1
> +#define RGA_SRC_VSCL_MODE_UP 2
> +
> +#define RGA_SRC_TRANS_ENABLE_R 1
> +#define RGA_SRC_TRANS_ENABLE_G 2
> +#define RGA_SRC_TRANS_ENABLE_B 4
> +#define RGA_SRC_TRANS_ENABLE_A 8
> +
> +#define RGA_SRC_BIC_COE_SELEC_CATROM 0
> +#define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
> +#define RGA_SRC_BIC_COE_SELEC_HERMITE 2
> +#define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
> +
> +#define RGA_DST_DITHER_MODE_888_TO_666 0
> +#define RGA_DST_DITHER_MODE_888_TO_565 1
> +#define RGA_DST_DITHER_MODE_888_TO_555 2
> +#define RGA_DST_DITHER_MODE_888_TO_444 3
> +
> +#define RGA_DST_CSC_MODE_BYPASS 0
> +#define RGA_DST_CSC_MODE_BT601_R0 1
> +#define RGA_DST_CSC_MODE_BT601_R1 2
> +#define RGA_DST_CSC_MODE_BT709_R0 3
> +
> +#define RGA_ALPHA_ROP_MODE_2 0
> +#define RGA_ALPHA_ROP_MODE_3 1
> +#define RGA_ALPHA_ROP_MODE_4 2
> +
> +#define RGA_ALPHA_SELECT_ALPHA 0
> +#define RGA_ALPHA_SELECT_ROP 1
> +
> +#define RGA_ALPHA_MASK_BIG_ENDIAN 0
> +#define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
> +
> +#define RGA_ALPHA_NORMAL 0
> +#define RGA_ALPHA_REVERSE 1
> +
> +#define RGA_ALPHA_BLEND_GLOBAL 0
> +#define RGA_ALPHA_BLEND_NORMAL 1
> +#define RGA_ALPHA_BLEND_MULTIPLY 2
> +
> +#define RGA_ALPHA_CAL_CUT 0
> +#define RGA_ALPHA_CAL_NORMAL 1
> +
> +#define RGA_ALPHA_FACTOR_ZERO 0
> +#define RGA_ALPHA_FACTOR_ONE 1
> +#define RGA_ALPHA_FACTOR_OTHER 2
> +#define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
> +#define RGA_ALPHA_FACTOR_SELF 4
> +
> +#define RGA_ALPHA_COLOR_NORMAL 0
> +#define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
> +
> +/* Registers union */
> +union rga_mode_ctrl {
> +	unsigned int val;
> +	struct {
> +		/* [0:2] */
> +		unsigned int render:3;
> +		/* [3:6] */
> +		unsigned int bitblt:1;
> +		unsigned int cf_rop4_pat:1;
> +		unsigned int alpha_zero_key:1;
> +		unsigned int gradient_sat:1;
> +		/* [7:31] */
> +		unsigned int reserved:25;
> +	} data;
> +};
> +
> +union rga_src_info {
> +	unsigned int val;
> +	struct {
> +		/* [0:3] */
> +		unsigned int format:4;
> +		/* [4:7] */
> +		unsigned int swap:3;
> +		unsigned int cp_endian:1;
> +		/* [8:17] */
> +		unsigned int csc_mode:2;
> +		unsigned int rot_mode:2;
> +		unsigned int mir_mode:2;
> +		unsigned int hscl_mode:2;
> +		unsigned int vscl_mode:2;
> +		/* [18:22] */
> +		unsigned int trans_mode:1;
> +		unsigned int trans_enable:4;
> +		/* [23:25] */
> +		unsigned int dither_up_en:1;
> +		unsigned int bic_coe_sel:2;
> +		/* [26:31] */
> +		unsigned int reserved:6;
> +	} data;
> +};
> +
> +union rga_src_vir_info {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int vir_width:15;
> +		unsigned int reserved:1;
> +		/* [16:25] */
> +		unsigned int vir_stride:10;
> +		/* [26:31] */
> +		unsigned int reserved1:6;
> +	} data;
> +};
> +
> +union rga_src_act_info {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int act_width:13;
> +		unsigned int reserved:3;
> +		/* [16:31] */
> +		unsigned int act_height:13;
> +		unsigned int reserved1:3;
> +	} data;
> +};
> +
> +union rga_src_x_factor {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int down_scale_factor:16;
> +		/* [16:31] */
> +		unsigned int up_scale_factor:16;
> +	} data;
> +};
> +
> +union rga_src_y_factor {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int down_scale_factor:16;
> +		/* [16:31] */
> +		unsigned int up_scale_factor:16;
> +	} data;
> +};
> +
> +/* Alpha / Red / Green / Blue */
> +union rga_src_cp_gr_color {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int gradient_x:16;
> +		/* [16:31] */
> +		unsigned int gradient_y:16;
> +	} data;
> +};
> +
> +union rga_src_transparency_color0 {
> +	unsigned int val;
> +	struct {
> +		/* [0:7] */
> +		unsigned int trans_rmin:8;
> +		/* [8:15] */
> +		unsigned int trans_gmin:8;
> +		/* [16:23] */
> +		unsigned int trans_bmin:8;
> +		/* [24:31] */
> +		unsigned int trans_amin:8;
> +	} data;
> +};
> +
> +union rga_src_transparency_color1 {
> +	unsigned int val;
> +	struct {
> +		/* [0:7] */
> +		unsigned int trans_rmax:8;
> +		/* [8:15] */
> +		unsigned int trans_gmax:8;
> +		/* [16:23] */
> +		unsigned int trans_bmax:8;
> +		/* [24:31] */
> +		unsigned int trans_amax:8;
> +	} data;
> +};
> +
> +union rga_dst_info {
> +	unsigned int val;
> +	struct {
> +		/* [0:3] */
> +		unsigned int format:4;
> +		/* [4:6] */
> +		unsigned int swap:3;
> +		/* [7:9] */
> +		unsigned int src1_format:3;
> +		/* [10:11] */
> +		unsigned int src1_swap:2;
> +		/* [12:15] */
> +		unsigned int dither_up_en:1;
> +		unsigned int dither_down_en:1;
> +		unsigned int dither_down_mode:2;
> +		/* [16:18] */
> +		unsigned int csc_mode:2;
> +		unsigned int csc_clip:1;
> +		/* [19:31] */
> +		unsigned int reserved:13;
> +	} data;
> +};
> +
> +union rga_dst_vir_info {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int vir_stride:15;
> +		unsigned int reserved:1;
> +		/* [16:31] */
> +		unsigned int src1_vir_stride:15;
> +		unsigned int reserved1:1;
> +	} data;
> +};
> +
> +union rga_dst_act_info {
> +	unsigned int val;
> +	struct {
> +		/* [0:15] */
> +		unsigned int act_width:12;
> +		unsigned int reserved:4;
> +		/* [16:31] */
> +		unsigned int act_height:12;
> +		unsigned int reserved1:4;
> +	} data;
> +};
> +
> +union rga_alpha_ctrl0 {
> +	unsigned int val;
> +	struct {
> +		/* [0:3] */
> +		unsigned int rop_en:1;
> +		unsigned int rop_select:1;
> +		unsigned int rop_mode:2;
> +		/* [4:11] */
> +		unsigned int src_fading_val:8;
> +		/* [12:20] */
> +		unsigned int dst_fading_val:8;
> +		unsigned int mask_endian:1;
> +		/* [21:31] */
> +		unsigned int reserved:11;
> +	} data;
> +};
> +
> +union rga_alpha_ctrl1 {
> +	unsigned int val;
> +	struct {
> +		/* [0:1] */
> +		unsigned int dst_color_m0:1;
> +		unsigned int src_color_m0:1;
> +		/* [2:7] */
> +		unsigned int dst_factor_m0:3;
> +		unsigned int src_factor_m0:3;
> +		/* [8:9] */
> +		unsigned int dst_alpha_cal_m0:1;
> +		unsigned int src_alpha_cal_m0:1;
> +		/* [10:13] */
> +		unsigned int dst_blend_m0:2;
> +		unsigned int src_blend_m0:2;
> +		/* [14:15] */
> +		unsigned int dst_alpha_m0:1;
> +		unsigned int src_alpha_m0:1;
> +		/* [16:21] */
> +		unsigned int dst_factor_m1:3;
> +		unsigned int src_factor_m1:3;
> +		/* [22:23] */
> +		unsigned int dst_alpha_cal_m1:1;
> +		unsigned int src_alpha_cal_m1:1;
> +		/* [24:27] */
> +		unsigned int dst_blend_m1:2;
> +		unsigned int src_blend_m1:2;
> +		/* [28:29] */
> +		unsigned int dst_alpha_m1:1;
> +		unsigned int src_alpha_m1:1;
> +		/* [30:31] */
> +		unsigned int reserved:2;
> +	} data;
> +};
> +
> +union rga_fading_ctrl {
> +	unsigned int val;
> +	struct {
> +		/* [0:7] */
> +		unsigned int fading_offset_r:8;
> +		/* [8:15] */
> +		unsigned int fading_offset_g:8;
> +		/* [16:23] */
> +		unsigned int fading_offset_b:8;
> +		/* [24:31] */
> +		unsigned int fading_en:1;
> +		unsigned int reserved:7;
> +	} data;
> +};
> +
> +union rga_pat_con {
> +	unsigned int val;
> +	struct {
> +		/* [0:7] */
> +		unsigned int width:8;
> +		/* [8:15] */
> +		unsigned int height:8;
> +		/* [16:23] */
> +		unsigned int offset_x:8;
> +		/* [24:31] */
> +		unsigned int offset_y:8;
> +	} data;
> +};
> +
> +#endif
> diff --git a/drivers/media/platform/rockchip-rga/rga.c b/drivers/media/platform/rockchip-rga/rga.c
> new file mode 100644
> index 0000000..5ed3a48
> --- /dev/null
> +++ b/drivers/media/platform/rockchip-rga/rga.c
> @@ -0,0 +1,1026 @@
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/debugfs.h>
> +#include <linux/delay.h>
> +#include <linux/fs.h>
> +#include <linux/interrupt.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/pm_runtime.h>
> +#include <linux/reset.h>
> +#include <linux/sched.h>
> +#include <linux/slab.h>
> +#include <linux/timer.h>
> +
> +#include <linux/platform_device.h>
> +#include <media/v4l2-device.h>
> +#include <media/v4l2-event.h>
> +#include <media/v4l2-ioctl.h>
> +#include <media/v4l2-mem2mem.h>
> +#include <media/videobuf2-dma-sg.h>
> +#include <media/videobuf2-v4l2.h>
> +
> +#include "rga-hw.h"
> +#include "rga.h"
> +
> +static void job_abort(void *prv)
> +{
> +	struct rga_ctx *ctx = prv;
> +	struct rockchip_rga *rga = ctx->rga;
> +
> +	if (!rga->curr)	/* No job currently running */
> +		return;
> +
> +	wait_event_timeout(rga->irq_queue,
> +			   !rga->curr, msecs_to_jiffies(RGA_TIMEOUT));
> +}
> +
> +static void device_run(void *prv)
> +{
> +	struct rga_ctx *ctx = prv;
> +	struct rockchip_rga *rga = ctx->rga;
> +	struct vb2_buffer *src, *dst;
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&rga->ctrl_lock, flags);
> +
> +	rga->curr = ctx;
> +
> +	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
> +	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
> +
> +	rga_buf_map(src);
> +	rga_buf_map(dst);
> +
> +	rga_cmd_set(ctx);
> +
> +	rga_start(rga);
> +
> +	spin_unlock_irqrestore(&rga->ctrl_lock, flags);
> +}
> +
> +static irqreturn_t rga_isr(int irq, void *prv)
> +{
> +	struct rockchip_rga *rga = prv;
> +	int intr;
> +
> +	intr = rga_read(rga, RGA_INT) & 0xf;
> +
> +	rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
> +
> +	if (intr & 0x04) {
> +		struct vb2_v4l2_buffer *src, *dst;
> +		struct rga_ctx *ctx = rga->curr;
> +
> +		BUG_ON(!ctx);
> +
> +		rga->curr = NULL;
> +
> +		src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
> +		dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
> +
> +		BUG_ON(!src);
> +		BUG_ON(!dst);
> +
> +		dst->timecode = src->timecode;
> +		dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
> +		dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
> +		dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
> +
> +		v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
> +		v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
> +		v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
> +
> +		wake_up(&rga->irq_queue);
> +	}
> +
> +	return IRQ_HANDLED;
> +}
> +
> +static struct v4l2_m2m_ops rga_m2m_ops = {
> +	.device_run = device_run,
> +	.job_abort = job_abort,
> +};
> +
> +static int
> +queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
> +{
> +	struct rga_ctx *ctx = priv;
> +	int ret;
> +
> +	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
> +	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
> +	src_vq->drv_priv = ctx;
> +	src_vq->ops = &rga_qops;
> +	src_vq->mem_ops = &vb2_dma_sg_memops;
> +	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
> +	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
> +	src_vq->lock = &ctx->rga->mutex;
> +	src_vq->dev = ctx->rga->v4l2_dev.dev;
> +
> +	ret = vb2_queue_init(src_vq);
> +	if (ret)
> +		return ret;
> +
> +	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
> +	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
> +	dst_vq->drv_priv = ctx;
> +	dst_vq->ops = &rga_qops;
> +	dst_vq->mem_ops = &vb2_dma_sg_memops;
> +	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
> +	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
> +	dst_vq->lock = &ctx->rga->mutex;
> +	dst_vq->dev = ctx->rga->v4l2_dev.dev;
> +
> +	return vb2_queue_init(dst_vq);
> +}
> +
> +static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
> +{
> +	struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
> +					   ctrl_handler);
> +	unsigned long flags;
> +
> +	spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
> +	switch (ctrl->id) {
> +	case V4L2_CID_PORTER_DUFF_MODE:
> +		ctx->op = ctrl->val;
> +		break;
> +	case V4L2_CID_HFLIP:
> +		ctx->hflip = ctrl->val;
> +		break;
> +	case V4L2_CID_VFLIP:
> +		ctx->vflip = ctrl->val;
> +		break;
> +	case V4L2_CID_ROTATE:
> +		ctx->rotate = ctrl->val;
> +		break;
> +	case V4L2_CID_BG_COLOR:
> +		ctx->fill_color = ctrl->val;
> +		break;
> +	}
> +	spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
> +	return 0;
> +}
> +
> +static const struct v4l2_ctrl_ops rga_ctrl_ops = {
> +	.s_ctrl = rga_s_ctrl,
> +};
> +
> +static int rga_setup_ctrls(struct rga_ctx *ctx)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +
> +	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 5);
> +
> +	v4l2_ctrl_new_std_menu(&ctx->ctrl_handler, &rga_ctrl_ops,
> +			       V4L2_CID_PORTER_DUFF_MODE,
> +			       V4L2_PORTER_DUFF_CLEAR, 0,
> +			       V4L2_PORTER_DUFF_SRC);
> +
> +	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
> +			  V4L2_CID_HFLIP, 0, 1, 1, 0);
> +
> +	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
> +			  V4L2_CID_VFLIP, 0, 1, 1, 0);
> +
> +	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
> +			  V4L2_CID_ROTATE, 0, 270, 90, 0);
> +
> +	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
> +			  V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
> +
> +	if (ctx->ctrl_handler.error) {
> +		int err = ctx->ctrl_handler.error;
> +
> +		v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
> +		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
> +		return err;
> +	}
> +
> +	return 0;
> +}
> +
> +struct rga_fmt formats[] = {
> +	{
> +		.fourcc = V4L2_PIX_FMT_ARGB32,
> +		.color_swap = RGA_COLOR_RB_SWAP,
> +		.hw_format = RGA_COLOR_FMT_ABGR8888,
> +		.depth = 32,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_XRGB32,
> +		.color_swap = RGA_COLOR_RB_SWAP,
> +		.hw_format = RGA_COLOR_FMT_XBGR8888,
> +		.depth = 32,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_ABGR32,
> +		.color_swap = RGA_COLOR_ALPHA_SWAP,
> +		.hw_format = RGA_COLOR_FMT_ABGR8888,
> +		.depth = 32,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_XBGR32,
> +		.color_swap = RGA_COLOR_ALPHA_SWAP,
> +		.hw_format = RGA_COLOR_FMT_XBGR8888,
> +		.depth = 32,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_RGB24,
> +		.color_swap = RGA_COLOR_RB_SWAP,
> +		.hw_format = RGA_COLOR_FMT_BGR888,
> +		.depth = 24,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_ARGB444,
> +		.color_swap = RGA_COLOR_RB_SWAP,
> +		.hw_format = RGA_COLOR_FMT_ABGR4444,
> +		.depth = 16,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_ARGB555,
> +		.color_swap = RGA_COLOR_RB_SWAP,
> +		.hw_format = RGA_COLOR_FMT_ABGR1555,
> +		.depth = 16,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_RGB565,
> +		.color_swap = RGA_COLOR_RB_SWAP,
> +		.hw_format = RGA_COLOR_FMT_BGR565,
> +		.depth = 16,
> +		.uv_factor = 1,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_NV21,
> +		.color_swap = RGA_COLOR_UV_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV420SP,
> +		.depth = 12,
> +		.uv_factor = 4,
> +		.y_div = 2,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_NV61,
> +		.color_swap = RGA_COLOR_UV_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV422SP,
> +		.depth = 16,
> +		.uv_factor = 2,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_NV12,
> +		.color_swap = RGA_COLOR_NONE_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV420SP,
> +		.depth = 12,
> +		.uv_factor = 4,
> +		.y_div = 2,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_NV16,
> +		.color_swap = RGA_COLOR_NONE_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV422SP,
> +		.depth = 16,
> +		.uv_factor = 2,
> +		.y_div = 1,
> +		.x_div = 1,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_YUV420,
> +		.color_swap = RGA_COLOR_NONE_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV420P,
> +		.depth = 12,
> +		.uv_factor = 4,
> +		.y_div = 2,
> +		.x_div = 2,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_YUV422P,
> +		.color_swap = RGA_COLOR_NONE_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV422P,
> +		.depth = 16,
> +		.uv_factor = 2,
> +		.y_div = 1,
> +		.x_div = 2,
> +	},
> +	{
> +		.fourcc = V4L2_PIX_FMT_YVU420,
> +		.color_swap = RGA_COLOR_UV_SWAP,
> +		.hw_format = RGA_COLOR_FMT_YUV420P,
> +		.depth = 12,
> +		.uv_factor = 4,
> +		.y_div = 2,
> +		.x_div = 2,
> +	},
> +};
> +
> +#define NUM_FORMATS ARRAY_SIZE(formats)
> +
> +struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
> +{
> +	unsigned int i;
> +
> +	for (i = 0; i < NUM_FORMATS; i++) {
> +		if (formats[i].fourcc == f->fmt.pix.pixelformat)
> +			return &formats[i];
> +	}
> +	return NULL;
> +}
> +
> +static struct rga_frame def_frame = {
> +	.width = DEFAULT_WIDTH,
> +	.height = DEFAULT_HEIGHT,
> +	.colorspace = V4L2_COLORSPACE_DEFAULT,
> +	.crop.left = 0,
> +	.crop.top = 0,
> +	.crop.width = DEFAULT_WIDTH,
> +	.crop.height = DEFAULT_HEIGHT,
> +	.fmt = &formats[0],
> +};
> +
> +struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
> +{
> +	switch (type) {
> +	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
> +		return &ctx->in;
> +	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
> +		return &ctx->out;
> +	default:
> +		return ERR_PTR(-EINVAL);
> +	}
> +}
> +
> +static int rga_open(struct file *file)
> +{
> +	struct rockchip_rga *rga = video_drvdata(file);
> +	struct rga_ctx *ctx = NULL;
> +	int ret = 0;
> +
> +	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
> +	if (!ctx)
> +		return -ENOMEM;
> +	ctx->rga = rga;
> +	/* Set default formats */
> +	ctx->in = def_frame;
> +	ctx->out = def_frame;
> +
> +	if (mutex_lock_interruptible(&rga->mutex)) {
> +		kfree(ctx);
> +		return -ERESTARTSYS;
> +	}
> +	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
> +	if (IS_ERR(ctx->fh.m2m_ctx)) {
> +		ret = PTR_ERR(ctx->fh.m2m_ctx);
> +		mutex_unlock(&rga->mutex);
> +		kfree(ctx);
> +		return ret;
> +	}
> +	v4l2_fh_init(&ctx->fh, video_devdata(file));
> +	file->private_data = &ctx->fh;
> +	v4l2_fh_add(&ctx->fh);
> +
> +	rga_setup_ctrls(ctx);
> +
> +	/* Write the default values to the ctx struct */
> +	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
> +
> +	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
> +	mutex_unlock(&rga->mutex);
> +
> +	return 0;
> +}
> +
> +static int rga_release(struct file *file)
> +{
> +	struct rga_ctx *ctx =
> +		container_of(file->private_data, struct rga_ctx, fh);
> +	struct rockchip_rga *rga = ctx->rga;
> +
> +	mutex_lock(&rga->mutex);
> +
> +	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
> +
> +	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
> +	v4l2_fh_del(&ctx->fh);
> +	v4l2_fh_exit(&ctx->fh);
> +	kfree(ctx);
> +
> +	mutex_unlock(&rga->mutex);
> +
> +	return 0;
> +}
> +
> +static const struct v4l2_file_operations rga_fops = {
> +	.owner = THIS_MODULE,
> +	.open = rga_open,
> +	.release = rga_release,
> +	.poll = v4l2_m2m_fop_poll,
> +	.unlocked_ioctl = video_ioctl2,
> +	.mmap = v4l2_m2m_fop_mmap,
> +};
> +
> +static int
> +vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
> +{
> +	strlcpy(cap->driver, RGA_NAME, sizeof(cap->driver));
> +	strlcpy(cap->card, "rockchip-rga", sizeof(cap->card));
> +	strlcpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
> +
> +	return 0;
> +}
> +
> +static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
> +{
> +	struct rga_fmt *fmt;
> +
> +	if (f->index >= NUM_FORMATS)
> +		return -EINVAL;
> +
> +	fmt = &formats[f->index];
> +	f->pixelformat = fmt->fourcc;
> +
> +	return 0;
> +}
> +
> +static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
> +{
> +	struct rga_ctx *ctx = prv;
> +	struct vb2_queue *vq;
> +	struct rga_frame *frm;
> +
> +	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
> +	if (!vq)
> +		return -EINVAL;
> +	frm = rga_get_frame(ctx, f->type);
> +	if (IS_ERR(frm))
> +		return PTR_ERR(frm);
> +
> +	f->fmt.pix.width = frm->width;
> +	f->fmt.pix.height = frm->height;
> +	f->fmt.pix.field = V4L2_FIELD_NONE;
> +	f->fmt.pix.pixelformat = frm->fmt->fourcc;
> +	f->fmt.pix.bytesperline = frm->stride;
> +	f->fmt.pix.sizeimage = frm->size;
> +	f->fmt.pix.colorspace = frm->colorspace;
> +
> +	return 0;
> +}
> +
> +static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
> +{
> +	struct rga_fmt *fmt;
> +
> +	fmt = rga_fmt_find(f);
> +	if (!fmt) {
> +		fmt = &formats[0];
> +		f->fmt.pix.pixelformat = fmt->fourcc;
> +	}
> +
> +	f->fmt.pix.field = V4L2_FIELD_NONE;
> +
> +	if (f->fmt.pix.width > MAX_WIDTH)
> +		f->fmt.pix.width = MAX_WIDTH;
> +	if (f->fmt.pix.height > MAX_HEIGHT)
> +		f->fmt.pix.height = MAX_HEIGHT;
> +
> +	if (f->fmt.pix.width < MIN_WIDTH)
> +		f->fmt.pix.width = MIN_WIDTH;
> +	if (f->fmt.pix.height < MIN_HEIGHT)
> +		f->fmt.pix.height = MIN_HEIGHT;
> +
> +	if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
> +		f->fmt.pix.bytesperline = f->fmt.pix.width;
> +	else
> +		f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
> +
> +	f->fmt.pix.sizeimage =
> +		f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
> +
> +	return 0;
> +}
> +
> +static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
> +{
> +	struct rga_ctx *ctx = prv;
> +	struct rockchip_rga *rga = ctx->rga;
> +	struct vb2_queue *vq;
> +	struct rga_frame *frm;
> +	struct rga_fmt *fmt;
> +	int ret = 0;
> +
> +	/* Adjust all values accordingly to the hardware capabilities
> +	 * and chosen format.
> +	 */
> +	ret = vidioc_try_fmt(file, prv, f);
> +	if (ret)
> +		return ret;
> +	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
> +	if (vb2_is_busy(vq)) {
> +		v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
> +		return -EBUSY;
> +	}
> +	frm = rga_get_frame(ctx, f->type);
> +	if (IS_ERR(frm))
> +		return PTR_ERR(frm);
> +	fmt = rga_fmt_find(f);
> +	if (!fmt)
> +		return -EINVAL;
> +	frm->width = f->fmt.pix.width;
> +	frm->height = f->fmt.pix.height;
> +	frm->size = f->fmt.pix.sizeimage;
> +	frm->fmt = fmt;
> +	frm->stride = f->fmt.pix.bytesperline;
> +	frm->colorspace = f->fmt.pix.colorspace;
> +
> +	/* Reset crop settings */
> +	frm->crop.left = 0;
> +	frm->crop.top = 0;
> +	frm->crop.width = frm->width;
> +	frm->crop.height = frm->height;
> +
> +	return 0;
> +}
> +
> +static int
> +vidioc_try_crop(struct rga_ctx *ctx, struct v4l2_selection *s)
> +{
> +	struct rockchip_rga *rga = ctx->rga;
> +	struct rga_frame *f;
> +
> +	f = rga_get_frame(ctx, s->type);
> +	if (IS_ERR(f))
> +		return PTR_ERR(f);
> +
> +	switch (s->target) {
> +	case V4L2_SEL_TGT_COMPOSE:
> +		/*
> +		 * COMPOSE target is only valid for capture buffer type, return
> +		 * error for output buffer type
> +		 */
> +		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)

I think '!= V4L2_BUF_TYPE_VIDEO_CAPTURE' makes more sense.

> +			return -EINVAL;
> +		break;
> +	case V4L2_SEL_TGT_CROP:
> +		/*
> +		 * CROP target is only valid for output buffer type, return
> +		 * error for capture buffer type
> +		 */
> +		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)

!= V4L2_BUF_TYPE_VIDEO_OUTPUT

> +			return -EINVAL;
> +		break;
> +	/*
> +	 * bound and default crop/compose targets are invalid targets to
> +	 * try/set
> +	 */
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	if (s->r.top < 0 || s->r.left < 0) {
> +		v4l2_err(&rga->v4l2_dev,
> +			 "doesn't support negative values for top & left.\n");

I'd make this v4l2_dbg.

> +		return -EINVAL;
> +	}
> +
> +	if (s->r.left + s->r.width > s->r.width ||
> +	    s->r.top + s->r.height > s->r.height ||

Sorry, is this right? This basically means the same as:

s->r.left != 0 || s->r.top != 0

I suspect you want to test against the current v4l2_pix_format
width and height since you compose into that buffer.

> +	    s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
> +		v4l2_err(&rga->v4l2_dev, "unsupport crop value.\n");

v4l2_dbg.

s/unsupport/unsupported/

> +		return -EINVAL;
> +	}
> +
> +	return 0;
> +}
> +
> +static int vidioc_g_selection(struct file *file, void *prv,
> +			      struct v4l2_selection *s)
> +{
> +	struct rga_ctx *ctx = prv;
> +	struct rga_frame *f;
> +	bool use_frame = false;
> +
> +	f = rga_get_frame(ctx, s->type);
> +	if (IS_ERR(f))
> +		return PTR_ERR(f);
> +
> +	switch (s->target) {
> +	case V4L2_SEL_TGT_COMPOSE_DEFAULT:
> +	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
> +		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)

Same comment here, invert these conditions.

> +			return -EINVAL;
> +		break;
> +	case V4L2_SEL_TGT_CROP_BOUNDS:
> +	case V4L2_SEL_TGT_CROP_DEFAULT:
> +		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
> +			return -EINVAL;
> +		break;
> +	case V4L2_SEL_TGT_COMPOSE:
> +		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
> +			return -EINVAL;
> +		use_frame = true;
> +		break;
> +	case V4L2_SEL_TGT_CROP:
> +		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
> +			return -EINVAL;
> +		use_frame = true;
> +		break;
> +	default:
> +		return -EINVAL;
> +	}
> +
> +	if (use_frame) {
> +		s->r = f->crop;
> +	} else {
> +		s->r.left = 0;
> +		s->r.top = 0;
> +		s->r.width = f->width;
> +		s->r.height = f->height;
> +	}
> +
> +	return 0;
> +}
> +
> +static int vidioc_s_selection(struct file *file, void *prv,
> +			      struct v4l2_selection *s)
> +{
> +	struct rga_ctx *ctx = prv;
> +	struct rga_frame *f;
> +	int ret = 0;
> +
> +	ret = vidioc_try_crop(ctx, s);
> +	if (ret)
> +		return ret;
> +
> +	f = rga_get_frame(ctx, s->type);
> +	if (IS_ERR(f))
> +		return PTR_ERR(f);
> +
> +	f->crop = s->r;
> +
> +	return ret;
> +}
> +
> +static const struct v4l2_ioctl_ops rga_ioctl_ops = {
> +	.vidioc_querycap = vidioc_querycap,
> +
> +	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
> +	.vidioc_g_fmt_vid_cap = vidioc_g_fmt,
> +	.vidioc_try_fmt_vid_cap = vidioc_try_fmt,
> +	.vidioc_s_fmt_vid_cap = vidioc_s_fmt,
> +
> +	.vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
> +	.vidioc_g_fmt_vid_out = vidioc_g_fmt,
> +	.vidioc_try_fmt_vid_out = vidioc_try_fmt,
> +	.vidioc_s_fmt_vid_out = vidioc_s_fmt,
> +
> +	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
> +	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
> +	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
> +	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
> +	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
> +	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
> +	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
> +
> +	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
> +	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
> +
> +	.vidioc_streamon = v4l2_m2m_ioctl_streamon,
> +	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
> +
> +	.vidioc_g_selection = vidioc_g_selection,
> +	.vidioc_s_selection = vidioc_s_selection,
> +};
> +
> +static struct video_device rga_videodev = {
> +	.name = "rockchip-rga",
> +	.fops = &rga_fops,
> +	.ioctl_ops = &rga_ioctl_ops,
> +	.minor = -1,
> +	.release = video_device_release,
> +	.vfl_dir = VFL_DIR_M2M,
> +	.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
> +};
> +
> +static int rga_enable_clocks(struct rockchip_rga *rga)
> +{
> +	int ret;
> +
> +	ret = clk_prepare_enable(rga->sclk);
> +	if (ret) {
> +		dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
> +		return ret;
> +	}
> +
> +	ret = clk_prepare_enable(rga->aclk);
> +	if (ret) {
> +		dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
> +		goto err_disable_sclk;
> +	}
> +
> +	ret = clk_prepare_enable(rga->hclk);
> +	if (ret) {
> +		dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
> +		goto err_disable_aclk;
> +	}
> +
> +	return 0;
> +
> +err_disable_sclk:
> +	clk_disable_unprepare(rga->sclk);
> +err_disable_aclk:
> +	clk_disable_unprepare(rga->aclk);
> +
> +	return ret;
> +}
> +
> +static void rga_disable_clocks(struct rockchip_rga *rga)
> +{
> +	clk_disable_unprepare(rga->sclk);
> +	clk_disable_unprepare(rga->hclk);
> +	clk_disable_unprepare(rga->aclk);
> +}
> +
> +static int rga_parse_dt(struct rockchip_rga *rga)
> +{
> +	struct reset_control *core_rst, *axi_rst, *ahb_rst;
> +
> +	core_rst = devm_reset_control_get(rga->dev, "core");
> +	if (IS_ERR(core_rst)) {
> +		dev_err(rga->dev, "failed to get core reset controller\n");
> +		return PTR_ERR(core_rst);
> +	}
> +
> +	axi_rst = devm_reset_control_get(rga->dev, "axi");
> +	if (IS_ERR(axi_rst)) {
> +		dev_err(rga->dev, "failed to get axi reset controller\n");
> +		return PTR_ERR(axi_rst);
> +	}
> +
> +	ahb_rst = devm_reset_control_get(rga->dev, "ahb");
> +	if (IS_ERR(ahb_rst)) {
> +		dev_err(rga->dev, "failed to get ahb reset controller\n");
> +		return PTR_ERR(ahb_rst);
> +	}
> +
> +	reset_control_assert(core_rst);
> +	udelay(1);
> +	reset_control_deassert(core_rst);
> +
> +	reset_control_assert(axi_rst);
> +	udelay(1);
> +	reset_control_deassert(axi_rst);
> +
> +	reset_control_assert(ahb_rst);
> +	udelay(1);
> +	reset_control_deassert(ahb_rst);
> +
> +	rga->sclk = devm_clk_get(rga->dev, "sclk");
> +	if (IS_ERR(rga->sclk)) {
> +		dev_err(rga->dev, "failed to get sclk clock\n");
> +		return PTR_ERR(rga->sclk);
> +	}
> +
> +	rga->aclk = devm_clk_get(rga->dev, "aclk");
> +	if (IS_ERR(rga->aclk)) {
> +		dev_err(rga->dev, "failed to get aclk clock\n");
> +		return PTR_ERR(rga->aclk);
> +	}
> +
> +	rga->hclk = devm_clk_get(rga->dev, "hclk");
> +	if (IS_ERR(rga->hclk)) {
> +		dev_err(rga->dev, "failed to get hclk clock\n");
> +		return PTR_ERR(rga->hclk);
> +	}
> +
> +	return 0;
> +}
> +
> +static int rga_probe(struct platform_device *pdev)
> +{
> +	struct rockchip_rga *rga;
> +	struct video_device *vfd;
> +	struct resource *res;
> +	int ret = 0;
> +	int irq;
> +
> +	if (!pdev->dev.of_node)
> +		return -ENODEV;
> +
> +	rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
> +	if (!rga)
> +		return -ENOMEM;
> +
> +	rga->dev = &pdev->dev;
> +	spin_lock_init(&rga->ctrl_lock);
> +	mutex_init(&rga->mutex);
> +
> +	init_waitqueue_head(&rga->irq_queue);
> +
> +	ret = rga_parse_dt(rga);
> +	if (ret)
> +		dev_err(&pdev->dev, "Unable to parse OF data\n");
> +
> +	pm_runtime_enable(rga->dev);
> +
> +	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
> +
> +	rga->regs = devm_ioremap_resource(rga->dev, res);
> +	if (IS_ERR(rga->regs)) {
> +		ret = PTR_ERR(rga->regs);
> +		goto err_put_clk;
> +	}
> +
> +	irq = platform_get_irq(pdev, 0);
> +	if (irq < 0) {
> +		dev_err(rga->dev, "failed to get irq\n");
> +		ret = irq;
> +		goto err_put_clk;
> +	}
> +
> +	ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
> +			       dev_name(rga->dev), rga);
> +	if (ret < 0) {
> +		dev_err(rga->dev, "failed to request irq\n");
> +		goto err_put_clk;
> +	}
> +
> +	ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
> +	if (ret)
> +		goto err_put_clk;
> +	vfd = video_device_alloc();
> +	if (!vfd) {
> +		v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
> +		ret = -ENOMEM;
> +		goto unreg_v4l2_dev;
> +	}
> +	*vfd = rga_videodev;
> +	vfd->lock = &rga->mutex;
> +	vfd->v4l2_dev = &rga->v4l2_dev;
> +
> +	video_set_drvdata(vfd, rga);
> +	snprintf(vfd->name, sizeof(vfd->name), "%s", rga_videodev.name);
> +	rga->vfd = vfd;
> +
> +	platform_set_drvdata(pdev, rga);
> +	rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
> +	if (IS_ERR(rga->m2m_dev)) {
> +		v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
> +		ret = PTR_ERR(rga->m2m_dev);
> +		goto unreg_video_dev;
> +	}
> +
> +	pm_runtime_get_sync(rga->dev);
> +
> +	rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
> +	rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
> +
> +	v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
> +		  rga->version.major, rga->version.minor);
> +
> +	pm_runtime_put(rga->dev);
> +
> +	/* Create CMD buffer */
> +	rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
> +					   &rga->cmdbuf_phy, GFP_KERNEL,
> +					   DMA_ATTR_WRITE_COMBINE);
> +
> +	rga->src_mmu_pages =
> +		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
> +	rga->dst_mmu_pages =
> +		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
> +
> +	def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
> +	def_frame.size = def_frame.stride * def_frame.height;
> +
> +	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
> +	if (ret) {
> +		v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
> +		goto rel_vdev;
> +	}
> +
> +	v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
> +		  vfd->name, video_device_node_name(vfd));
> +
> +	return 0;
> +
> +rel_vdev:
> +	video_device_release(vfd);
> +unreg_video_dev:
> +	video_unregister_device(rga->vfd);
> +unreg_v4l2_dev:
> +	v4l2_device_unregister(&rga->v4l2_dev);
> +err_put_clk:
> +	pm_runtime_disable(rga->dev);
> +
> +	return ret;
> +}
> +
> +static int rga_remove(struct platform_device *pdev)
> +{
> +	struct rockchip_rga *rga = platform_get_drvdata(pdev);
> +
> +	dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, &rga->cmdbuf_virt,
> +		       rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
> +
> +	free_pages((unsigned long)rga->src_mmu_pages, 3);
> +	free_pages((unsigned long)rga->dst_mmu_pages, 3);
> +
> +	v4l2_info(&rga->v4l2_dev, "Removing\n");
> +
> +	v4l2_m2m_release(rga->m2m_dev);
> +	video_unregister_device(rga->vfd);
> +	v4l2_device_unregister(&rga->v4l2_dev);
> +
> +	pm_runtime_disable(rga->dev);
> +
> +	return 0;
> +}
> +
> +#ifdef CONFIG_PM
> +static int rga_runtime_suspend(struct device *dev)
> +{
> +	struct rockchip_rga *rga = dev_get_drvdata(dev);
> +
> +	rga_disable_clocks(rga);
> +
> +	return 0;
> +}
> +
> +static int rga_runtime_resume(struct device *dev)
> +{
> +	struct rockchip_rga *rga = dev_get_drvdata(dev);
> +
> +	return rga_enable_clocks(rga);
> +}
> +#endif
> +
> +static const struct dev_pm_ops rga_pm = {
> +	SET_RUNTIME_PM_OPS(rga_runtime_suspend,
> +			   rga_runtime_resume, NULL)
> +};
> +
> +static const struct of_device_id rockchip_rga_match[] = {
> +	{
> +		.compatible = "rockchip,rk3288-rga",
> +	},
> +	{
> +		.compatible = "rockchip,rk3399-rga",
> +	},
> +	{},
> +};
> +
> +MODULE_DEVICE_TABLE(of, rockchip_rga_match);
> +
> +static struct platform_driver rga_pdrv = {
> +	.probe = rga_probe,
> +	.remove = rga_remove,
> +	.driver = {
> +		.name = RGA_NAME,
> +		.pm = &rga_pm,
> +		.of_match_table = rockchip_rga_match,
> +	},
> +};
> +
> +module_platform_driver(rga_pdrv);
> +
> +MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
> +MODULE_DESCRIPTION("Rockchip Raster 2d Grapphic Acceleration Unit");
> +MODULE_LICENSE("GPL");
> diff --git a/drivers/media/platform/rockchip-rga/rga.h b/drivers/media/platform/rockchip-rga/rga.h
> new file mode 100644
> index 0000000..c7d35b8
> --- /dev/null
> +++ b/drivers/media/platform/rockchip-rga/rga.h
> @@ -0,0 +1,110 @@
> +/*
> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + */
> +#ifndef __RGA_H__
> +#define __RGA_H__
> +
> +#include <linux/platform_device.h>
> +#include <media/videobuf2-v4l2.h>
> +#include <media/v4l2-ctrls.h>
> +#include <media/v4l2-device.h>
> +
> +#define RGA_NAME "rockchip-rga"
> +
> +struct rga_fmt {
> +	u32 fourcc;
> +	int depth;
> +	u8 uv_factor;
> +	u8 y_div;
> +	u8 x_div;
> +	u8 color_swap;
> +	u8 hw_format;
> +};
> +
> +struct rga_frame {
> +	/* Original dimensions */
> +	u32 width;
> +	u32 height;
> +	u32 colorspace;
> +
> +	/* Crop */
> +	struct v4l2_rect crop;
> +
> +	/* Image format */
> +	struct rga_fmt *fmt;
> +
> +	/* Variables that can calculated once and reused */
> +	u32 stride;
> +	u32 size;
> +};
> +
> +struct rockchip_rga_version {
> +	u32 major;
> +	u32 minor;
> +};
> +
> +struct rga_ctx {
> +	struct v4l2_fh fh;
> +	struct rockchip_rga *rga;
> +	struct rga_frame in;
> +	struct rga_frame out;
> +	struct v4l2_ctrl_handler ctrl_handler;
> +
> +	/* Control values */
> +	u32 op;
> +	u32 hflip;
> +	u32 vflip;
> +	u32 rotate;
> +	u32 fill_color;
> +};
> +
> +struct rockchip_rga {
> +	struct v4l2_device v4l2_dev;
> +	struct v4l2_m2m_dev *m2m_dev;
> +	struct video_device *vfd;
> +
> +	struct device *dev;
> +	struct regmap *grf;
> +	void __iomem *regs;
> +	struct clk *sclk;
> +	struct clk *aclk;
> +	struct clk *hclk;
> +	struct rockchip_rga_version version;
> +
> +	struct mutex mutex;
> +	spinlock_t ctrl_lock;
> +
> +	wait_queue_head_t irq_queue;
> +
> +	struct rga_ctx *curr;
> +	dma_addr_t cmdbuf_phy;
> +	void *cmdbuf_virt;
> +	unsigned int *src_mmu_pages;
> +	unsigned int *dst_mmu_pages;
> +};
> +
> +struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type);
> +
> +/* RGA Buffers Manage Part */
> +extern const struct vb2_ops rga_qops;
> +void rga_buf_map(struct vb2_buffer *vb);
> +
> +/* RGA Hardware Part */
> +void rga_write(struct rockchip_rga *rga, u32 reg, u32 value);
> +u32 rga_read(struct rockchip_rga *rga, u32 reg);
> +void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask);
> +void rga_start(struct rockchip_rga *rga);
> +
> +void rga_cmd_set(struct rga_ctx *ctx);
> +
> +#endif
> 

So this looks good, except for the fairly small comments above.

As mentioned earlier, I need the v4l2-compliance output and I'll look at what is
currently failing there. That should be fixed either in the driver or in the
compliance test (if the problem is there).

One other question: did you actually test crop/compose? Handling selection
correctly is always tricky, so make sure this is tested.

Regards,

	Hans
Jacob Chen Aug. 25, 2017, 2:57 p.m. UTC | #5 
Hi Hans,

2017-08-21 22:16 GMT+08:00 Hans Verkuil <hverkuil@xs4all.nl>:
> Hi Jacob,
>
> On 08/03/2017 07:23 AM, Jacob Chen wrote:
>> Rockchip RGA is a separate 2D raster graphic acceleration unit. It
>> accelerates 2D graphics operations, such as point/line drawing, image
>> scaling, rotation, BitBLT, alpha blending and image blur/sharpness
>>
>> The drvier is mostly based on s5p-g2d v4l2 m2m driver
>> And supports various operations from the rendering pipeline.
>>  - copy
>>  - fast solid color fill
>>  - rotation
>>  - flip
>>  - alpha blending
>>
>> The code in rga-hw.c is used to configure regs according to operations
>> The code in rga-buf.c is used to create private mmu table for RGA.
>>
>> changes in V7:
>> - fix some warning reported by "checkpatch --strict"
>>
>> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
>
> Can you post the v4l2-compliance output? I gather that there is at least one
> colorspace-related error that appears to be a v4l2-compliance bug, so I'd
> like to see the exact error it gives. I'll see if I can fix it so this driver
> has a clean compliance output.
>

OK, i will post it.

> I apologize that this driver probably won't make 4.14. Too much to review...
>

It doesn't matter,
I'm still writing the userspace for this driver ,
At peresent this driver might have a lot of bugs, since i didn't test
it much in production environment .

> I hope to do the v7 review within a week.
>
> Regards,
>
>         Hans
Jacob Chen Sept. 11, 2017, 10:53 a.m. UTC | #6 
Hi Hans,

2017-08-25 20:09 GMT+08:00 Hans Verkuil <hverkuil@xs4all.nl>:
> Hi Jacob,
>
> As promised, some more (small) review comments below.
>
> On 03/08/17 07:23, Jacob Chen wrote:
>> Rockchip RGA is a separate 2D raster graphic acceleration unit. It
>> accelerates 2D graphics operations, such as point/line drawing, image
>> scaling, rotation, BitBLT, alpha blending and image blur/sharpness
>>
>> The drvier is mostly based on s5p-g2d v4l2 m2m driver
>
> driver
>
>> And supports various operations from the rendering pipeline.
>>  - copy
>>  - fast solid color fill
>>  - rotation
>>  - flip
>>  - alpha blending
>>
>> The code in rga-hw.c is used to configure regs according to operations
>> The code in rga-buf.c is used to create private mmu table for RGA.
>>
>> changes in V7:
>> - fix some warning reported by "checkpatch --strict"
>>
>> Signed-off-by: Jacob Chen <jacob-chen@iotwrt.com>
>> ---
>>  drivers/media/platform/Kconfig                |   11 +
>>  drivers/media/platform/Makefile               |    2 +
>>  drivers/media/platform/rockchip-rga/Makefile  |    3 +
>>  drivers/media/platform/rockchip-rga/rga-buf.c |  155 ++++
>>  drivers/media/platform/rockchip-rga/rga-hw.c  |  670 ++++++++++++++++
>>  drivers/media/platform/rockchip-rga/rga-hw.h  |  437 +++++++++++
>>  drivers/media/platform/rockchip-rga/rga.c     | 1026 +++++++++++++++++++++++++
>>  drivers/media/platform/rockchip-rga/rga.h     |  110 +++
>>  8 files changed, 2414 insertions(+)
>>  create mode 100644 drivers/media/platform/rockchip-rga/Makefile
>>  create mode 100644 drivers/media/platform/rockchip-rga/rga-buf.c
>>  create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.c
>>  create mode 100644 drivers/media/platform/rockchip-rga/rga-hw.h
>>  create mode 100644 drivers/media/platform/rockchip-rga/rga.c
>>  create mode 100644 drivers/media/platform/rockchip-rga/rga.h
>>
>> diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
>> index 041cb80a..d0d1a21 100644
>> --- a/drivers/media/platform/Kconfig
>> +++ b/drivers/media/platform/Kconfig
>> @@ -427,6 +427,17 @@ config VIDEO_RENESAS_VSP1
>>         To compile this driver as a module, choose M here: the module
>>         will be called vsp1.
>>
>> +config VIDEO_ROCKCHIP_RGA
>> +     tristate "Rockchip Raster 2d Grapphic Acceleration Unit"
>> +     depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
>> +     depends on ARCH_ROCKCHIP || COMPILE_TEST
>> +     select VIDEOBUF2_DMA_SG
>> +     select V4L2_MEM2MEM_DEV
>> +     default n
>> +     ---help---
>> +       This is a v4l2 driver for Rockchip SOC RGA2
>> +       2d graphics accelerator.
>> +
>>  config VIDEO_TI_VPE
>>       tristate "TI VPE (Video Processing Engine) driver"
>>       depends on VIDEO_DEV && VIDEO_V4L2
>> diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
>> index 63303d6..baf83060 100644
>> --- a/drivers/media/platform/Makefile
>> +++ b/drivers/media/platform/Makefile
>> @@ -57,6 +57,8 @@ obj-$(CONFIG_VIDEO_RENESAS_FDP1)    += rcar_fdp1.o
>>  obj-$(CONFIG_VIDEO_RENESAS_JPU)      += rcar_jpu.o
>>  obj-$(CONFIG_VIDEO_RENESAS_VSP1)     += vsp1/
>>
>> +obj-$(CONFIG_VIDEO_ROCKCHIP_RGA)     += rockchip-rga/
>> +
>>  obj-y        += omap/
>>
>>  obj-$(CONFIG_VIDEO_AM437X_VPFE)              += am437x/
>> diff --git a/drivers/media/platform/rockchip-rga/Makefile b/drivers/media/platform/rockchip-rga/Makefile
>> new file mode 100644
>> index 0000000..92fe254
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip-rga/Makefile
>> @@ -0,0 +1,3 @@
>> +rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
>> +
>> +obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
>> diff --git a/drivers/media/platform/rockchip-rga/rga-buf.c b/drivers/media/platform/rockchip-rga/rga-buf.c
>> new file mode 100644
>> index 0000000..6a9fd2c
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip-rga/rga-buf.c
>> @@ -0,0 +1,155 @@
>> +/*
>> + * Copyright (C) 2017 Fuzhou Rockchip Electronics Co.Ltd
>> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/pm_runtime.h>
>> +
>> +#include <media/v4l2-device.h>
>> +#include <media/v4l2-ioctl.h>
>> +#include <media/v4l2-mem2mem.h>
>> +#include <media/videobuf2-dma-sg.h>
>> +#include <media/videobuf2-v4l2.h>
>> +
>> +#include "rga-hw.h"
>> +#include "rga.h"
>> +
>> +static int
>> +rga_queue_setup(struct vb2_queue *vq,
>> +             unsigned int *nbuffers, unsigned int *nplanes,
>> +             unsigned int sizes[], struct device *alloc_devs[])
>> +{
>> +     struct rga_ctx *ctx = vb2_get_drv_priv(vq);
>> +     struct rga_frame *f = rga_get_frame(ctx, vq->type);
>> +
>> +     if (IS_ERR(f))
>> +             return PTR_ERR(f);
>> +
>> +     if (*nplanes)
>> +             return sizes[0] < f->size ? -EINVAL : 0;
>> +
>> +     sizes[0] = f->size;
>> +     *nplanes = 1;
>> +
>> +     return 0;
>> +}
>> +
>> +static int rga_buf_prepare(struct vb2_buffer *vb)
>> +{
>> +     struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
>> +     struct rga_frame *f = rga_get_frame(ctx, vb->vb2_queue->type);
>> +
>> +     if (IS_ERR(f))
>> +             return PTR_ERR(f);
>> +
>> +     vb2_set_plane_payload(vb, 0, f->size);
>> +
>> +     return 0;
>> +}
>> +
>> +static void rga_buf_queue(struct vb2_buffer *vb)
>> +{
>> +     struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
>> +     struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
>> +
>> +     v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
>> +}
>> +
>> +static int rga_buf_start_streaming(struct vb2_queue *q, unsigned int count)
>> +{
>> +     struct rga_ctx *ctx = vb2_get_drv_priv(q);
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     int ret, i;
>> +
>> +     ret = pm_runtime_get_sync(rga->dev);
>> +
>> +     if (ret < 0) {
>> +             for (i = 0; i < q->num_buffers; ++i) {
>> +                     if (q->bufs[i]->state == VB2_BUF_STATE_ACTIVE) {
>> +                             v4l2_m2m_buf_done(to_vb2_v4l2_buffer(q->bufs[i]),
>> +                                             VB2_BUF_STATE_QUEUED);
>> +                     }
>> +             }
>> +
>> +             return ret;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static void rga_buf_stop_streaming(struct vb2_queue *q)
>> +{
>> +     struct rga_ctx *ctx = vb2_get_drv_priv(q);
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     struct vb2_v4l2_buffer *vbuf;
>> +
>> +     for (;;) {
>> +             if (V4L2_TYPE_IS_OUTPUT(q->type))
>> +                     vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
>> +             else
>> +                     vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
>> +             if (!vbuf)
>> +                     break;
>> +             v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
>> +     }
>> +
>> +     pm_runtime_put(rga->dev);
>> +}
>> +
>> +const struct vb2_ops rga_qops = {
>> +     .queue_setup = rga_queue_setup,
>> +     .buf_prepare = rga_buf_prepare,
>> +     .buf_queue = rga_buf_queue,
>> +     .wait_prepare = vb2_ops_wait_prepare,
>> +     .wait_finish = vb2_ops_wait_finish,
>> +     .start_streaming = rga_buf_start_streaming,
>> +     .stop_streaming = rga_buf_stop_streaming,
>> +};
>> +
>> +/* RGA MMU is a 1-Level MMU, so it can't be used through the IOMMU API.
>> + * We use it more like a scatter-gather list.
>> + */
>> +void rga_buf_map(struct vb2_buffer *vb)
>> +{
>> +     struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     struct sg_table *sgt;
>> +     struct scatterlist *sgl;
>> +     unsigned int *pages;
>> +     unsigned int address, len, i, p;
>> +     unsigned int mapped_size = 0;
>> +
>> +     if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
>> +             pages = rga->src_mmu_pages;
>> +     else
>> +             pages = rga->dst_mmu_pages;
>> +
>> +     /* Create local MMU table for RGA */
>> +     sgt = vb2_plane_cookie(vb, 0);
>> +
>> +     for_each_sg(sgt->sgl, sgl, sgt->nents, i) {
>> +             len = sg_dma_len(sgl) >> PAGE_SHIFT;
>> +             address = sg_phys(sgl);
>> +
>> +             for (p = 0; p < len; p++) {
>> +                     dma_addr_t phys = address + (p << PAGE_SHIFT);
>> +
>> +                     pages[mapped_size + p] = phys;
>> +             }
>> +
>> +             mapped_size += len;
>> +     }
>> +
>> +     /* sync local MMU table for RGA */
>> +     dma_sync_single_for_device(rga->dev, virt_to_phys(pages),
>> +                                8 * PAGE_SIZE, DMA_BIDIRECTIONAL);
>> +}
>> diff --git a/drivers/media/platform/rockchip-rga/rga-hw.c b/drivers/media/platform/rockchip-rga/rga-hw.c
>> new file mode 100644
>> index 0000000..5b7ee58
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip-rga/rga-hw.c
>> @@ -0,0 +1,670 @@
>> +/*
>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/pm_runtime.h>
>> +
>> +#include "rga-hw.h"
>> +#include "rga.h"
>> +
>> +enum e_rga_start_pos {
>> +     LT = 0,
>> +     LB = 1,
>> +     RT = 2,
>> +     RB = 3,
>> +};
>> +
>> +struct rga_addr_offset {
>> +     unsigned int y_off;
>> +     unsigned int u_off;
>> +     unsigned int v_off;
>> +};
>> +
>> +struct rga_corners_addr_offset {
>> +     struct rga_addr_offset left_top;
>> +     struct rga_addr_offset right_top;
>> +     struct rga_addr_offset left_bottom;
>> +     struct rga_addr_offset right_bottom;
>> +};
>> +
>> +static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)
>> +{
>> +     /*
>> +      * The rga hw scaling factor is a normalized inverse of the
>> +      * scaling factor.
>> +      * For example: When source width is 100 and destination width is 200
>> +      * (scaling of 2x), then the hw factor is NC * 100 / 200.
>> +      * The normalization factor (NC) is 2^16 = 0x10000.
>> +      */
>> +
>> +     return (src > dst) ? ((dst << 16) / src) : ((src << 16) / dst);
>> +}
>> +
>> +static struct rga_corners_addr_offset
>> +rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,
>> +                 unsigned int w, unsigned int h)
>> +{
>> +     struct rga_corners_addr_offset offsets;
>> +     struct rga_addr_offset *lt, *lb, *rt, *rb;
>> +     unsigned int x_div = 0,
>> +                  y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;
>> +
>> +     lt = &offsets.left_top;
>> +     lb = &offsets.left_bottom;
>> +     rt = &offsets.right_top;
>> +     rb = &offsets.right_bottom;
>> +
>> +     x_div = frm->fmt->x_div;
>> +     y_div = frm->fmt->y_div;
>> +     uv_factor = frm->fmt->uv_factor;
>> +     uv_stride = frm->stride / x_div;
>> +     pixel_width = frm->stride / frm->width;
>> +
>> +     lt->y_off = y * frm->stride + x * pixel_width;
>> +     lt->u_off =
>> +             frm->width * frm->height + (y / y_div) * uv_stride + x / x_div;
>> +     lt->v_off = lt->u_off + frm->width * frm->height / uv_factor;
>> +
>> +     lb->y_off = lt->y_off + (h - 1) * frm->stride;
>> +     lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride;
>> +     lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride;
>> +
>> +     rt->y_off = lt->y_off + (w - 1) * pixel_width;
>> +     rt->u_off = lt->u_off + w / x_div - 1;
>> +     rt->v_off = lt->v_off + w / x_div - 1;
>> +
>> +     rb->y_off = lb->y_off + (w - 1) * pixel_width;
>> +     rb->u_off = lb->u_off + w / x_div - 1;
>> +     rb->v_off = lb->v_off + w / x_div - 1;
>> +
>> +     return offsets;
>> +}
>> +
>> +static struct rga_addr_offset *rga_lookup_draw_pos(struct
>> +             rga_corners_addr_offset
>> +             * offsets, u32 rotate_mode,
>> +             u32 mirr_mode)
>> +{
>> +     static enum e_rga_start_pos rot_mir_point_matrix[4][4] = {
>> +             {
>> +                     LT, RT, LB, RB,
>> +             },
>> +             {
>> +                     RT, LT, RB, LB,
>> +             },
>> +             {
>> +                     RB, LB, RT, LT,
>> +             },
>> +             {
>> +                     LB, RB, LT, RT,
>> +             },
>> +     };
>> +
>> +     if (!offsets)
>> +             return NULL;
>> +
>> +     switch (rot_mir_point_matrix[rotate_mode][mirr_mode]) {
>> +     case LT:
>> +             return &offsets->left_top;
>> +     case LB:
>> +             return &offsets->left_bottom;
>> +     case RT:
>> +             return &offsets->right_top;
>> +     case RB:
>> +             return &offsets->right_bottom;
>> +     }
>> +
>> +     return NULL;
>> +}
>> +
>> +static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     u32 *dest = rga->cmdbuf_virt;
>> +     unsigned int reg;
>> +
>> +     reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;
>> +     dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
>> +
>> +     reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
>> +     dest[reg >> 2] |= 0x7;
>> +}
>> +
>> +static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     u32 *dest = rga->cmdbuf_virt;
>> +     unsigned int reg;
>> +
>> +     reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;
>> +     dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
>> +
>> +     reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
>> +     dest[reg >> 2] |= 0x7 << 4;
>> +}
>> +
>> +static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     u32 *dest = rga->cmdbuf_virt;
>> +     unsigned int reg;
>> +
>> +     reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;
>> +     dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
>> +
>> +     reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
>> +     dest[reg >> 2] |= 0x7 << 8;
>> +}
>> +
>> +static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     u32 *dest = rga->cmdbuf_virt;
>> +     unsigned int scale_dst_w, scale_dst_h;
>> +     unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
>> +     union rga_src_info src_info;
>> +     union rga_dst_info dst_info;
>> +     union rga_src_x_factor x_factor;
>> +     union rga_src_y_factor y_factor;
>> +     union rga_src_vir_info src_vir_info;
>> +     union rga_src_act_info src_act_info;
>> +     union rga_dst_vir_info dst_vir_info;
>> +     union rga_dst_act_info dst_act_info;
>> +
>> +     struct rga_addr_offset *dst_offset;
>> +     struct rga_corners_addr_offset offsets;
>> +     struct rga_corners_addr_offset src_offsets;
>> +
>> +     src_h = ctx->in.crop.height;
>> +     src_w = ctx->in.crop.width;
>> +     src_x = ctx->in.crop.left;
>> +     src_y = ctx->in.crop.top;
>> +     dst_h = ctx->out.crop.height;
>> +     dst_w = ctx->out.crop.width;
>> +     dst_x = ctx->out.crop.left;
>> +     dst_y = ctx->out.crop.top;
>> +
>> +     src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
>> +     dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
>> +     x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
>> +     y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
>> +     src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
>> +     src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
>> +     dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
>> +     dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
>> +
>> +     src_info.data.format = ctx->in.fmt->hw_format;
>> +     src_info.data.swap = ctx->in.fmt->color_swap;
>> +     dst_info.data.format = ctx->out.fmt->hw_format;
>> +     dst_info.data.swap = ctx->out.fmt->color_swap;
>> +
>> +     if (ctx->in.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
>> +             if (ctx->out.fmt->hw_format < RGA_COLOR_FMT_YUV422SP) {
>> +                     switch (ctx->in.colorspace) {
>> +                     case V4L2_COLORSPACE_REC709:
>> +                             src_info.data.csc_mode =
>> +                                     RGA_SRC_CSC_MODE_BT709_R0;
>> +                             break;
>> +                     default:
>> +                             src_info.data.csc_mode =
>> +                                     RGA_SRC_CSC_MODE_BT601_R0;
>> +                             break;
>> +                     }
>> +             }
>> +     }
>> +
>> +     if (ctx->out.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
>> +             switch (ctx->out.colorspace) {
>> +             case V4L2_COLORSPACE_REC709:
>> +                     dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
>> +                     break;
>> +             default:
>> +                     dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
>> +                     break;
>> +             }
>> +     }
>> +
>> +     if (ctx->op == V4L2_PORTER_DUFF_CLEAR) {
>> +             /*
>> +              * Configure the target color to foreground color.
>> +              */
>> +             dest[(RGA_SRC_FG_COLOR - RGA_MODE_BASE_REG) >> 2] =
>> +                     ctx->fill_color;
>> +             dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
>> +             dst_act_info.data.act_height = dst_h - 1;
>> +             dst_act_info.data.act_width = dst_w - 1;
>> +
>> +             offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y,
>> +                                           dst_w, dst_h);
>> +             dst_offset = &offsets.left_top;
>> +
>> +             goto write_dst;
>> +     }
>> +
>> +     if (ctx->vflip)
>> +             src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
>> +
>> +     if (ctx->hflip)
>> +             src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
>> +
>> +     switch (ctx->rotate) {
>> +     case 90:
>> +             src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
>> +             break;
>> +     case 180:
>> +             src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
>> +             break;
>> +     case 270:
>> +             src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
>> +             break;
>> +     default:
>> +             src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
>> +             break;
>> +     }
>> +
>> +     /*
>> +      * Cacluate the up/down scaling mode/factor.
>> +      *
>> +      * RGA used to scale the picture first, and then rotate second,
>> +      * so we need to swap the w/h when rotate degree is 90/270.
>> +      */
>> +     if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
>> +         src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
>> +             if (rga->version.major == 0 || rga->version.minor == 0) {
>> +                     if (dst_w == src_h)
>> +                             src_h -= 8;
>> +                     if (abs(src_w - dst_h) < 16)
>> +                             src_w -= 16;
>> +             }
>> +
>> +             scale_dst_h = dst_w;
>> +             scale_dst_w = dst_h;
>> +     } else {
>> +             scale_dst_w = dst_w;
>> +             scale_dst_h = dst_h;
>> +     }
>> +
>> +     if (src_w == scale_dst_w) {
>> +             src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
>> +             x_factor.val = 0;
>> +     } else if (src_w > scale_dst_w) {
>> +             src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
>> +             x_factor.data.down_scale_factor =
>> +                     rga_get_scaling(src_w, scale_dst_w) + 1;
>> +     } else {
>> +             src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
>> +             x_factor.data.up_scale_factor =
>> +                     rga_get_scaling(src_w - 1, scale_dst_w - 1);
>> +     }
>> +
>> +     if (src_h == scale_dst_h) {
>> +             src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
>> +             y_factor.val = 0;
>> +     } else if (src_h > scale_dst_h) {
>> +             src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
>> +             y_factor.data.down_scale_factor =
>> +                     rga_get_scaling(src_h, scale_dst_h) + 1;
>> +     } else {
>> +             src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
>> +             y_factor.data.up_scale_factor =
>> +                     rga_get_scaling(src_h - 1, scale_dst_h - 1);
>> +     }
>> +
>> +     /*
>> +      * Cacluate the framebuffer virtual strides and active size,
>> +      * note that the step of vir_stride / vir_width is 4 byte words
>> +      */
>> +     src_vir_info.data.vir_stride = ctx->in.stride >> 2;
>> +     src_vir_info.data.vir_width = ctx->in.stride >> 2;
>> +
>> +     src_act_info.data.act_height = src_h - 1;
>> +     src_act_info.data.act_width = src_w - 1;
>> +
>> +     dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
>> +     dst_act_info.data.act_height = dst_h - 1;
>> +     dst_act_info.data.act_width = dst_w - 1;
>> +
>> +     /*
>> +      * Cacluate the source framebuffer base address with offset pixel.
>> +      */
>> +     src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
>> +                                       src_w, src_h);
>> +
>> +     /*
>> +      * Configure the dest framebuffer base address with pixel offset.
>> +      */
>> +     offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
>> +     dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
>> +                                      src_info.data.mir_mode);
>> +
>> +     dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
>> +             src_offsets.left_top.y_off;
>> +     dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
>> +             src_offsets.left_top.u_off;
>> +     dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
>> +             src_offsets.left_top.v_off;
>> +
>> +     dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
>> +     dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
>> +     dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
>> +     dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
>> +
>> +     dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
>> +
>> +write_dst:
>> +     dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
>> +             dst_offset->y_off;
>> +     dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
>> +             dst_offset->u_off;
>> +     dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
>> +             dst_offset->v_off;
>> +
>> +     dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
>> +     dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
>> +
>> +     dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
>> +}
>> +
>> +static void rga_cmd_set_mode(struct rga_ctx *ctx)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     u32 *dest = rga->cmdbuf_virt;
>> +     union rga_mode_ctrl mode;
>> +     union rga_alpha_ctrl0 alpha_ctrl0;
>> +     union rga_alpha_ctrl1 alpha_ctrl1;
>> +
>> +     mode.val = 0;
>> +     alpha_ctrl0.val = 0;
>> +     alpha_ctrl1.val = 0;
>> +
>> +     switch (ctx->op) {
>> +     case V4L2_PORTER_DUFF_CLEAR:
>> +             mode.data.gradient_sat = 1;
>> +             mode.data.render = RGA_MODE_RENDER_RECTANGLE_FILL;
>> +             mode.data.cf_rop4_pat = RGA_MODE_CF_ROP4_SOLID;
>> +             mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
>> +             break;
>> +     case V4L2_PORTER_DUFF_DST:
>> +     case V4L2_PORTER_DUFF_DSTATOP:
>> +     case V4L2_PORTER_DUFF_DSTIN:
>> +     case V4L2_PORTER_DUFF_DSTOUT:
>> +     case V4L2_PORTER_DUFF_DSTOVER:
>> +     case V4L2_PORTER_DUFF_SRCATOP:
>> +     case V4L2_PORTER_DUFF_SRCIN:
>> +     case V4L2_PORTER_DUFF_SRCOUT:
>> +     case V4L2_PORTER_DUFF_SRCOVER:
>> +             mode.data.gradient_sat = 1;
>> +             mode.data.render = RGA_MODE_RENDER_BITBLT;
>> +             mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
>> +
>> +             alpha_ctrl0.data.rop_en = 1;
>> +             alpha_ctrl0.data.rop_mode = RGA_ALPHA_ROP_MODE_3;
>> +             alpha_ctrl0.data.rop_select = RGA_ALPHA_SELECT_ALPHA;
>> +
>> +             alpha_ctrl1.data.dst_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
>> +             break;
>> +     default:
>> +             mode.data.gradient_sat = 1;
>> +             mode.data.render = RGA_MODE_RENDER_BITBLT;
>> +             mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
>> +             break;
>> +     }
>> +
>> +     switch (ctx->op) {
>> +     case V4L2_PORTER_DUFF_DST:
>> +             /* A=Dst.a */
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
>> +
>> +             /* C=Dst.c */
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
>> +             break;
>> +     case V4L2_PORTER_DUFF_DSTATOP:
>> +             /* A=Src.a */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
>> +
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             /* C=Src.a*Dst.c+Src.c*(1.0-Dst.a) */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
>> +             break;
>> +     case V4L2_PORTER_DUFF_DSTIN:
>> +             /* A=Dst.a*Src.a */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
>> +
>> +             /* C=Dst.c*Src.a */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
>> +             break;
>> +     case V4L2_PORTER_DUFF_DSTOUT:
>> +             /* A=Dst.a*(1.0-Src.a) */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             /* C=Dst.c*(1.0-Src.a) */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +             break;
>> +     case V4L2_PORTER_DUFF_DSTOVER:
>> +             /* A=Src.a+Dst.a*(1.0-Src.a) */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             /* C=Dst.c+Src.c*(1.0-Dst.a) */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
>> +             break;
>> +     case V4L2_PORTER_DUFF_SRCATOP:
>> +             /* A=Dst.a */
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
>> +
>> +             /* C=Dst.a*Src.c+Dst.c*(1.0-Src.a) */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +             break;
>> +     case V4L2_PORTER_DUFF_SRCIN:
>> +             /* A=Src.a*Dst.a */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
>> +
>> +             /* C=Src.c*Dst.a */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
>> +             break;
>> +     case V4L2_PORTER_DUFF_SRCOUT:
>> +             /* A=Src.a*(1.0-Dst.a) */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
>> +
>> +             /* C=Src.c*(1.0-Dst.a) */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
>> +             break;
>> +     case V4L2_PORTER_DUFF_SRCOVER:
>> +             /* A=Src.a+Dst.a*(1.0-Src.a) */
>> +             alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
>> +
>> +             alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +
>> +             /* C=Src.c+Dst.c*(1.0-Src.a) */
>> +             alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ONE;
>> +
>> +             alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
>> +             alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
>> +             alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
>> +             alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
>> +             break;
>> +     default:
>> +             break;
>> +     }
>> +
>> +     dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
>> +     dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
>> +
>> +     dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
>> +}
>> +
>> +void rga_cmd_set(struct rga_ctx *ctx)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +
>> +     memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
>> +
>> +     if (ctx->op != V4L2_PORTER_DUFF_CLEAR) {
>> +             rga_cmd_set_src_addr(ctx, rga->src_mmu_pages);
>> +             /*
>> +              * Due to hardware bug,
>> +              * src1 mmu also should be configured when using alpha blending.
>> +              */
>> +             rga_cmd_set_src1_addr(ctx, rga->dst_mmu_pages);
>> +     }
>> +     rga_cmd_set_dst_addr(ctx, rga->dst_mmu_pages);
>> +     rga_cmd_set_mode(ctx);
>> +
>> +     rga_cmd_set_trans_info(ctx);
>> +
>> +     rga_write(rga, RGA_CMD_BASE, rga->cmdbuf_phy);
>> +}
>> +
>> +void rga_write(struct rockchip_rga *rga, u32 reg, u32 value)
>> +{
>> +     writel(value, rga->regs + reg);
>> +}
>> +
>> +u32 rga_read(struct rockchip_rga *rga, u32 reg)
>> +{
>> +     return readl(rga->regs + reg);
>> +}
>> +
>> +void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
>> +{
>> +     u32 temp = rga_read(rga, reg) & ~(mask);
>> +
>> +     temp |= val & mask;
>> +     rga_write(rga, reg, temp);
>> +}
>> +
>> +void rga_start(struct rockchip_rga *rga)
>> +{
>> +     /* sync CMD buf for RGA */
>> +     dma_sync_single_for_device(rga->dev, rga->cmdbuf_phy,
>> +                                PAGE_SIZE, DMA_BIDIRECTIONAL);
>> +
>> +     rga_write(rga, RGA_SYS_CTRL, 0x00);
>> +
>> +     rga_write(rga, RGA_SYS_CTRL, 0x22);
>> +
>> +     rga_write(rga, RGA_INT, 0x600);
>> +
>> +     rga_write(rga, RGA_CMD_CTRL, 0x1);
>> +}
>> diff --git a/drivers/media/platform/rockchip-rga/rga-hw.h b/drivers/media/platform/rockchip-rga/rga-hw.h
>> new file mode 100644
>> index 0000000..a8b6353
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip-rga/rga-hw.h
>> @@ -0,0 +1,437 @@
>> +/*
>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +#ifndef __RGA_HW_H__
>> +#define __RGA_HW_H__
>> +
>> +#define RGA_CMDBUF_SIZE 0x20
>> +
>> +/* Hardware limits */
>> +#define MAX_WIDTH 8192
>> +#define MAX_HEIGHT 8192
>> +
>> +#define MIN_WIDTH 34
>> +#define MIN_HEIGHT 34
>> +
>> +#define DEFAULT_WIDTH 100
>> +#define DEFAULT_HEIGHT 100
>> +
>> +#define RGA_TIMEOUT 500
>> +
>> +/* Registers address */
>> +#define RGA_SYS_CTRL 0x0000
>> +#define RGA_CMD_CTRL 0x0004
>> +#define RGA_CMD_BASE 0x0008
>> +#define RGA_INT 0x0010
>> +#define RGA_MMU_CTRL0 0x0014
>> +#define RGA_VERSION_INFO 0x0028
>> +
>> +#define RGA_MODE_BASE_REG 0x0100
>> +#define RGA_MODE_MAX_REG 0x017C
>> +
>> +#define RGA_MODE_CTRL 0x0100
>> +#define RGA_SRC_INFO 0x0104
>> +#define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
>> +#define RGA_SRC_CB_BASE_ADDR 0x010c
>> +#define RGA_SRC_CR_BASE_ADDR 0x0110
>> +#define RGA_SRC1_RGB_BASE_ADDR 0x0114
>> +#define RGA_SRC_VIR_INFO 0x0118
>> +#define RGA_SRC_ACT_INFO 0x011c
>> +#define RGA_SRC_X_FACTOR 0x0120
>> +#define RGA_SRC_Y_FACTOR 0x0124
>> +#define RGA_SRC_BG_COLOR 0x0128
>> +#define RGA_SRC_FG_COLOR 0x012c
>> +#define RGA_SRC_TR_COLOR0 0x0130
>> +#define RGA_SRC_TR_COLOR1 0x0134
>> +
>> +#define RGA_DST_INFO 0x0138
>> +#define RGA_DST_Y_RGB_BASE_ADDR 0x013c
>> +#define RGA_DST_CB_BASE_ADDR 0x0140
>> +#define RGA_DST_CR_BASE_ADDR 0x0144
>> +#define RGA_DST_VIR_INFO 0x0148
>> +#define RGA_DST_ACT_INFO 0x014c
>> +
>> +#define RGA_ALPHA_CTRL0 0x0150
>> +#define RGA_ALPHA_CTRL1 0x0154
>> +#define RGA_FADING_CTRL 0x0158
>> +#define RGA_PAT_CON 0x015c
>> +#define RGA_ROP_CON0 0x0160
>> +#define RGA_ROP_CON1 0x0164
>> +#define RGA_MASK_BASE 0x0168
>> +
>> +#define RGA_MMU_CTRL1 0x016C
>> +#define RGA_MMU_SRC_BASE 0x0170
>> +#define RGA_MMU_SRC1_BASE 0x0174
>> +#define RGA_MMU_DST_BASE 0x0178
>> +
>> +/* Registers value */
>> +#define RGA_MODE_RENDER_BITBLT 0
>> +#define RGA_MODE_RENDER_COLOR_PALETTE 1
>> +#define RGA_MODE_RENDER_RECTANGLE_FILL 2
>> +#define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
>> +
>> +#define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
>> +#define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
>> +
>> +#define RGA_MODE_CF_ROP4_SOLID 0
>> +#define RGA_MODE_CF_ROP4_PATTERN 1
>> +
>> +#define RGA_COLOR_FMT_ABGR8888 0
>> +#define RGA_COLOR_FMT_XBGR8888 1
>> +#define RGA_COLOR_FMT_BGR888 2
>> +#define RGA_COLOR_FMT_BGR565 4
>> +#define RGA_COLOR_FMT_ABGR1555 5
>> +#define RGA_COLOR_FMT_ABGR4444 6
>> +#define RGA_COLOR_FMT_YUV422SP 8
>> +#define RGA_COLOR_FMT_YUV422P 9
>> +#define RGA_COLOR_FMT_YUV420SP 10
>> +#define RGA_COLOR_FMT_YUV420P 11
>> +/* SRC_COLOR Palette */
>> +#define RGA_COLOR_FMT_CP_1BPP 12
>> +#define RGA_COLOR_FMT_CP_2BPP 13
>> +#define RGA_COLOR_FMT_CP_4BPP 14
>> +#define RGA_COLOR_FMT_CP_8BPP 15
>> +#define RGA_COLOR_FMT_MASK 15
>> +
>> +#define RGA_COLOR_NONE_SWAP 0
>> +#define RGA_COLOR_RB_SWAP 1
>> +#define RGA_COLOR_ALPHA_SWAP 2
>> +#define RGA_COLOR_UV_SWAP 4
>> +
>> +#define RGA_SRC_CSC_MODE_BYPASS 0
>> +#define RGA_SRC_CSC_MODE_BT601_R0 1
>> +#define RGA_SRC_CSC_MODE_BT601_R1 2
>> +#define RGA_SRC_CSC_MODE_BT709_R0 3
>> +#define RGA_SRC_CSC_MODE_BT709_R1 4
>> +
>> +#define RGA_SRC_ROT_MODE_0_DEGREE 0
>> +#define RGA_SRC_ROT_MODE_90_DEGREE 1
>> +#define RGA_SRC_ROT_MODE_180_DEGREE 2
>> +#define RGA_SRC_ROT_MODE_270_DEGREE 3
>> +
>> +#define RGA_SRC_MIRR_MODE_NO 0
>> +#define RGA_SRC_MIRR_MODE_X 1
>> +#define RGA_SRC_MIRR_MODE_Y 2
>> +#define RGA_SRC_MIRR_MODE_X_Y 3
>> +
>> +#define RGA_SRC_HSCL_MODE_NO 0
>> +#define RGA_SRC_HSCL_MODE_DOWN 1
>> +#define RGA_SRC_HSCL_MODE_UP 2
>> +
>> +#define RGA_SRC_VSCL_MODE_NO 0
>> +#define RGA_SRC_VSCL_MODE_DOWN 1
>> +#define RGA_SRC_VSCL_MODE_UP 2
>> +
>> +#define RGA_SRC_TRANS_ENABLE_R 1
>> +#define RGA_SRC_TRANS_ENABLE_G 2
>> +#define RGA_SRC_TRANS_ENABLE_B 4
>> +#define RGA_SRC_TRANS_ENABLE_A 8
>> +
>> +#define RGA_SRC_BIC_COE_SELEC_CATROM 0
>> +#define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
>> +#define RGA_SRC_BIC_COE_SELEC_HERMITE 2
>> +#define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
>> +
>> +#define RGA_DST_DITHER_MODE_888_TO_666 0
>> +#define RGA_DST_DITHER_MODE_888_TO_565 1
>> +#define RGA_DST_DITHER_MODE_888_TO_555 2
>> +#define RGA_DST_DITHER_MODE_888_TO_444 3
>> +
>> +#define RGA_DST_CSC_MODE_BYPASS 0
>> +#define RGA_DST_CSC_MODE_BT601_R0 1
>> +#define RGA_DST_CSC_MODE_BT601_R1 2
>> +#define RGA_DST_CSC_MODE_BT709_R0 3
>> +
>> +#define RGA_ALPHA_ROP_MODE_2 0
>> +#define RGA_ALPHA_ROP_MODE_3 1
>> +#define RGA_ALPHA_ROP_MODE_4 2
>> +
>> +#define RGA_ALPHA_SELECT_ALPHA 0
>> +#define RGA_ALPHA_SELECT_ROP 1
>> +
>> +#define RGA_ALPHA_MASK_BIG_ENDIAN 0
>> +#define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
>> +
>> +#define RGA_ALPHA_NORMAL 0
>> +#define RGA_ALPHA_REVERSE 1
>> +
>> +#define RGA_ALPHA_BLEND_GLOBAL 0
>> +#define RGA_ALPHA_BLEND_NORMAL 1
>> +#define RGA_ALPHA_BLEND_MULTIPLY 2
>> +
>> +#define RGA_ALPHA_CAL_CUT 0
>> +#define RGA_ALPHA_CAL_NORMAL 1
>> +
>> +#define RGA_ALPHA_FACTOR_ZERO 0
>> +#define RGA_ALPHA_FACTOR_ONE 1
>> +#define RGA_ALPHA_FACTOR_OTHER 2
>> +#define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
>> +#define RGA_ALPHA_FACTOR_SELF 4
>> +
>> +#define RGA_ALPHA_COLOR_NORMAL 0
>> +#define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
>> +
>> +/* Registers union */
>> +union rga_mode_ctrl {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:2] */
>> +             unsigned int render:3;
>> +             /* [3:6] */
>> +             unsigned int bitblt:1;
>> +             unsigned int cf_rop4_pat:1;
>> +             unsigned int alpha_zero_key:1;
>> +             unsigned int gradient_sat:1;
>> +             /* [7:31] */
>> +             unsigned int reserved:25;
>> +     } data;
>> +};
>> +
>> +union rga_src_info {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:3] */
>> +             unsigned int format:4;
>> +             /* [4:7] */
>> +             unsigned int swap:3;
>> +             unsigned int cp_endian:1;
>> +             /* [8:17] */
>> +             unsigned int csc_mode:2;
>> +             unsigned int rot_mode:2;
>> +             unsigned int mir_mode:2;
>> +             unsigned int hscl_mode:2;
>> +             unsigned int vscl_mode:2;
>> +             /* [18:22] */
>> +             unsigned int trans_mode:1;
>> +             unsigned int trans_enable:4;
>> +             /* [23:25] */
>> +             unsigned int dither_up_en:1;
>> +             unsigned int bic_coe_sel:2;
>> +             /* [26:31] */
>> +             unsigned int reserved:6;
>> +     } data;
>> +};
>> +
>> +union rga_src_vir_info {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int vir_width:15;
>> +             unsigned int reserved:1;
>> +             /* [16:25] */
>> +             unsigned int vir_stride:10;
>> +             /* [26:31] */
>> +             unsigned int reserved1:6;
>> +     } data;
>> +};
>> +
>> +union rga_src_act_info {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int act_width:13;
>> +             unsigned int reserved:3;
>> +             /* [16:31] */
>> +             unsigned int act_height:13;
>> +             unsigned int reserved1:3;
>> +     } data;
>> +};
>> +
>> +union rga_src_x_factor {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int down_scale_factor:16;
>> +             /* [16:31] */
>> +             unsigned int up_scale_factor:16;
>> +     } data;
>> +};
>> +
>> +union rga_src_y_factor {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int down_scale_factor:16;
>> +             /* [16:31] */
>> +             unsigned int up_scale_factor:16;
>> +     } data;
>> +};
>> +
>> +/* Alpha / Red / Green / Blue */
>> +union rga_src_cp_gr_color {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int gradient_x:16;
>> +             /* [16:31] */
>> +             unsigned int gradient_y:16;
>> +     } data;
>> +};
>> +
>> +union rga_src_transparency_color0 {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:7] */
>> +             unsigned int trans_rmin:8;
>> +             /* [8:15] */
>> +             unsigned int trans_gmin:8;
>> +             /* [16:23] */
>> +             unsigned int trans_bmin:8;
>> +             /* [24:31] */
>> +             unsigned int trans_amin:8;
>> +     } data;
>> +};
>> +
>> +union rga_src_transparency_color1 {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:7] */
>> +             unsigned int trans_rmax:8;
>> +             /* [8:15] */
>> +             unsigned int trans_gmax:8;
>> +             /* [16:23] */
>> +             unsigned int trans_bmax:8;
>> +             /* [24:31] */
>> +             unsigned int trans_amax:8;
>> +     } data;
>> +};
>> +
>> +union rga_dst_info {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:3] */
>> +             unsigned int format:4;
>> +             /* [4:6] */
>> +             unsigned int swap:3;
>> +             /* [7:9] */
>> +             unsigned int src1_format:3;
>> +             /* [10:11] */
>> +             unsigned int src1_swap:2;
>> +             /* [12:15] */
>> +             unsigned int dither_up_en:1;
>> +             unsigned int dither_down_en:1;
>> +             unsigned int dither_down_mode:2;
>> +             /* [16:18] */
>> +             unsigned int csc_mode:2;
>> +             unsigned int csc_clip:1;
>> +             /* [19:31] */
>> +             unsigned int reserved:13;
>> +     } data;
>> +};
>> +
>> +union rga_dst_vir_info {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int vir_stride:15;
>> +             unsigned int reserved:1;
>> +             /* [16:31] */
>> +             unsigned int src1_vir_stride:15;
>> +             unsigned int reserved1:1;
>> +     } data;
>> +};
>> +
>> +union rga_dst_act_info {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:15] */
>> +             unsigned int act_width:12;
>> +             unsigned int reserved:4;
>> +             /* [16:31] */
>> +             unsigned int act_height:12;
>> +             unsigned int reserved1:4;
>> +     } data;
>> +};
>> +
>> +union rga_alpha_ctrl0 {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:3] */
>> +             unsigned int rop_en:1;
>> +             unsigned int rop_select:1;
>> +             unsigned int rop_mode:2;
>> +             /* [4:11] */
>> +             unsigned int src_fading_val:8;
>> +             /* [12:20] */
>> +             unsigned int dst_fading_val:8;
>> +             unsigned int mask_endian:1;
>> +             /* [21:31] */
>> +             unsigned int reserved:11;
>> +     } data;
>> +};
>> +
>> +union rga_alpha_ctrl1 {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:1] */
>> +             unsigned int dst_color_m0:1;
>> +             unsigned int src_color_m0:1;
>> +             /* [2:7] */
>> +             unsigned int dst_factor_m0:3;
>> +             unsigned int src_factor_m0:3;
>> +             /* [8:9] */
>> +             unsigned int dst_alpha_cal_m0:1;
>> +             unsigned int src_alpha_cal_m0:1;
>> +             /* [10:13] */
>> +             unsigned int dst_blend_m0:2;
>> +             unsigned int src_blend_m0:2;
>> +             /* [14:15] */
>> +             unsigned int dst_alpha_m0:1;
>> +             unsigned int src_alpha_m0:1;
>> +             /* [16:21] */
>> +             unsigned int dst_factor_m1:3;
>> +             unsigned int src_factor_m1:3;
>> +             /* [22:23] */
>> +             unsigned int dst_alpha_cal_m1:1;
>> +             unsigned int src_alpha_cal_m1:1;
>> +             /* [24:27] */
>> +             unsigned int dst_blend_m1:2;
>> +             unsigned int src_blend_m1:2;
>> +             /* [28:29] */
>> +             unsigned int dst_alpha_m1:1;
>> +             unsigned int src_alpha_m1:1;
>> +             /* [30:31] */
>> +             unsigned int reserved:2;
>> +     } data;
>> +};
>> +
>> +union rga_fading_ctrl {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:7] */
>> +             unsigned int fading_offset_r:8;
>> +             /* [8:15] */
>> +             unsigned int fading_offset_g:8;
>> +             /* [16:23] */
>> +             unsigned int fading_offset_b:8;
>> +             /* [24:31] */
>> +             unsigned int fading_en:1;
>> +             unsigned int reserved:7;
>> +     } data;
>> +};
>> +
>> +union rga_pat_con {
>> +     unsigned int val;
>> +     struct {
>> +             /* [0:7] */
>> +             unsigned int width:8;
>> +             /* [8:15] */
>> +             unsigned int height:8;
>> +             /* [16:23] */
>> +             unsigned int offset_x:8;
>> +             /* [24:31] */
>> +             unsigned int offset_y:8;
>> +     } data;
>> +};
>> +
>> +#endif
>> diff --git a/drivers/media/platform/rockchip-rga/rga.c b/drivers/media/platform/rockchip-rga/rga.c
>> new file mode 100644
>> index 0000000..5ed3a48
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip-rga/rga.c
>> @@ -0,0 +1,1026 @@
>> +/*
>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +
>> +#include <linux/clk.h>
>> +#include <linux/debugfs.h>
>> +#include <linux/delay.h>
>> +#include <linux/fs.h>
>> +#include <linux/interrupt.h>
>> +#include <linux/module.h>
>> +#include <linux/of.h>
>> +#include <linux/pm_runtime.h>
>> +#include <linux/reset.h>
>> +#include <linux/sched.h>
>> +#include <linux/slab.h>
>> +#include <linux/timer.h>
>> +
>> +#include <linux/platform_device.h>
>> +#include <media/v4l2-device.h>
>> +#include <media/v4l2-event.h>
>> +#include <media/v4l2-ioctl.h>
>> +#include <media/v4l2-mem2mem.h>
>> +#include <media/videobuf2-dma-sg.h>
>> +#include <media/videobuf2-v4l2.h>
>> +
>> +#include "rga-hw.h"
>> +#include "rga.h"
>> +
>> +static void job_abort(void *prv)
>> +{
>> +     struct rga_ctx *ctx = prv;
>> +     struct rockchip_rga *rga = ctx->rga;
>> +
>> +     if (!rga->curr) /* No job currently running */
>> +             return;
>> +
>> +     wait_event_timeout(rga->irq_queue,
>> +                        !rga->curr, msecs_to_jiffies(RGA_TIMEOUT));
>> +}
>> +
>> +static void device_run(void *prv)
>> +{
>> +     struct rga_ctx *ctx = prv;
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     struct vb2_buffer *src, *dst;
>> +     unsigned long flags;
>> +
>> +     spin_lock_irqsave(&rga->ctrl_lock, flags);
>> +
>> +     rga->curr = ctx;
>> +
>> +     src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
>> +     dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
>> +
>> +     rga_buf_map(src);
>> +     rga_buf_map(dst);
>> +
>> +     rga_cmd_set(ctx);
>> +
>> +     rga_start(rga);
>> +
>> +     spin_unlock_irqrestore(&rga->ctrl_lock, flags);
>> +}
>> +
>> +static irqreturn_t rga_isr(int irq, void *prv)
>> +{
>> +     struct rockchip_rga *rga = prv;
>> +     int intr;
>> +
>> +     intr = rga_read(rga, RGA_INT) & 0xf;
>> +
>> +     rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
>> +
>> +     if (intr & 0x04) {
>> +             struct vb2_v4l2_buffer *src, *dst;
>> +             struct rga_ctx *ctx = rga->curr;
>> +
>> +             BUG_ON(!ctx);
>> +
>> +             rga->curr = NULL;
>> +
>> +             src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
>> +             dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
>> +
>> +             BUG_ON(!src);
>> +             BUG_ON(!dst);
>> +
>> +             dst->timecode = src->timecode;
>> +             dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
>> +             dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
>> +             dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
>> +
>> +             v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
>> +             v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
>> +             v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
>> +
>> +             wake_up(&rga->irq_queue);
>> +     }
>> +
>> +     return IRQ_HANDLED;
>> +}
>> +
>> +static struct v4l2_m2m_ops rga_m2m_ops = {
>> +     .device_run = device_run,
>> +     .job_abort = job_abort,
>> +};
>> +
>> +static int
>> +queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
>> +{
>> +     struct rga_ctx *ctx = priv;
>> +     int ret;
>> +
>> +     src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
>> +     src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
>> +     src_vq->drv_priv = ctx;
>> +     src_vq->ops = &rga_qops;
>> +     src_vq->mem_ops = &vb2_dma_sg_memops;
>> +     src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
>> +     src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
>> +     src_vq->lock = &ctx->rga->mutex;
>> +     src_vq->dev = ctx->rga->v4l2_dev.dev;
>> +
>> +     ret = vb2_queue_init(src_vq);
>> +     if (ret)
>> +             return ret;
>> +
>> +     dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
>> +     dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
>> +     dst_vq->drv_priv = ctx;
>> +     dst_vq->ops = &rga_qops;
>> +     dst_vq->mem_ops = &vb2_dma_sg_memops;
>> +     dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
>> +     dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
>> +     dst_vq->lock = &ctx->rga->mutex;
>> +     dst_vq->dev = ctx->rga->v4l2_dev.dev;
>> +
>> +     return vb2_queue_init(dst_vq);
>> +}
>> +
>> +static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
>> +{
>> +     struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
>> +                                        ctrl_handler);
>> +     unsigned long flags;
>> +
>> +     spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
>> +     switch (ctrl->id) {
>> +     case V4L2_CID_PORTER_DUFF_MODE:
>> +             ctx->op = ctrl->val;
>> +             break;
>> +     case V4L2_CID_HFLIP:
>> +             ctx->hflip = ctrl->val;
>> +             break;
>> +     case V4L2_CID_VFLIP:
>> +             ctx->vflip = ctrl->val;
>> +             break;
>> +     case V4L2_CID_ROTATE:
>> +             ctx->rotate = ctrl->val;
>> +             break;
>> +     case V4L2_CID_BG_COLOR:
>> +             ctx->fill_color = ctrl->val;
>> +             break;
>> +     }
>> +     spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
>> +     return 0;
>> +}
>> +
>> +static const struct v4l2_ctrl_ops rga_ctrl_ops = {
>> +     .s_ctrl = rga_s_ctrl,
>> +};
>> +
>> +static int rga_setup_ctrls(struct rga_ctx *ctx)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +
>> +     v4l2_ctrl_handler_init(&ctx->ctrl_handler, 5);
>> +
>> +     v4l2_ctrl_new_std_menu(&ctx->ctrl_handler, &rga_ctrl_ops,
>> +                            V4L2_CID_PORTER_DUFF_MODE,
>> +                            V4L2_PORTER_DUFF_CLEAR, 0,
>> +                            V4L2_PORTER_DUFF_SRC);
>> +
>> +     v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
>> +                       V4L2_CID_HFLIP, 0, 1, 1, 0);
>> +
>> +     v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
>> +                       V4L2_CID_VFLIP, 0, 1, 1, 0);
>> +
>> +     v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
>> +                       V4L2_CID_ROTATE, 0, 270, 90, 0);
>> +
>> +     v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
>> +                       V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
>> +
>> +     if (ctx->ctrl_handler.error) {
>> +             int err = ctx->ctrl_handler.error;
>> +
>> +             v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
>> +             v4l2_ctrl_handler_free(&ctx->ctrl_handler);
>> +             return err;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +struct rga_fmt formats[] = {
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_ARGB32,
>> +             .color_swap = RGA_COLOR_RB_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_ABGR8888,
>> +             .depth = 32,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_XRGB32,
>> +             .color_swap = RGA_COLOR_RB_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_XBGR8888,
>> +             .depth = 32,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_ABGR32,
>> +             .color_swap = RGA_COLOR_ALPHA_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_ABGR8888,
>> +             .depth = 32,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_XBGR32,
>> +             .color_swap = RGA_COLOR_ALPHA_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_XBGR8888,
>> +             .depth = 32,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_RGB24,
>> +             .color_swap = RGA_COLOR_RB_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_BGR888,
>> +             .depth = 24,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_ARGB444,
>> +             .color_swap = RGA_COLOR_RB_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_ABGR4444,
>> +             .depth = 16,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_ARGB555,
>> +             .color_swap = RGA_COLOR_RB_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_ABGR1555,
>> +             .depth = 16,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_RGB565,
>> +             .color_swap = RGA_COLOR_RB_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_BGR565,
>> +             .depth = 16,
>> +             .uv_factor = 1,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_NV21,
>> +             .color_swap = RGA_COLOR_UV_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV420SP,
>> +             .depth = 12,
>> +             .uv_factor = 4,
>> +             .y_div = 2,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_NV61,
>> +             .color_swap = RGA_COLOR_UV_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV422SP,
>> +             .depth = 16,
>> +             .uv_factor = 2,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_NV12,
>> +             .color_swap = RGA_COLOR_NONE_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV420SP,
>> +             .depth = 12,
>> +             .uv_factor = 4,
>> +             .y_div = 2,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_NV16,
>> +             .color_swap = RGA_COLOR_NONE_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV422SP,
>> +             .depth = 16,
>> +             .uv_factor = 2,
>> +             .y_div = 1,
>> +             .x_div = 1,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_YUV420,
>> +             .color_swap = RGA_COLOR_NONE_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV420P,
>> +             .depth = 12,
>> +             .uv_factor = 4,
>> +             .y_div = 2,
>> +             .x_div = 2,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_YUV422P,
>> +             .color_swap = RGA_COLOR_NONE_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV422P,
>> +             .depth = 16,
>> +             .uv_factor = 2,
>> +             .y_div = 1,
>> +             .x_div = 2,
>> +     },
>> +     {
>> +             .fourcc = V4L2_PIX_FMT_YVU420,
>> +             .color_swap = RGA_COLOR_UV_SWAP,
>> +             .hw_format = RGA_COLOR_FMT_YUV420P,
>> +             .depth = 12,
>> +             .uv_factor = 4,
>> +             .y_div = 2,
>> +             .x_div = 2,
>> +     },
>> +};
>> +
>> +#define NUM_FORMATS ARRAY_SIZE(formats)
>> +
>> +struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
>> +{
>> +     unsigned int i;
>> +
>> +     for (i = 0; i < NUM_FORMATS; i++) {
>> +             if (formats[i].fourcc == f->fmt.pix.pixelformat)
>> +                     return &formats[i];
>> +     }
>> +     return NULL;
>> +}
>> +
>> +static struct rga_frame def_frame = {
>> +     .width = DEFAULT_WIDTH,
>> +     .height = DEFAULT_HEIGHT,
>> +     .colorspace = V4L2_COLORSPACE_DEFAULT,
>> +     .crop.left = 0,
>> +     .crop.top = 0,
>> +     .crop.width = DEFAULT_WIDTH,
>> +     .crop.height = DEFAULT_HEIGHT,
>> +     .fmt = &formats[0],
>> +};
>> +
>> +struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
>> +{
>> +     switch (type) {
>> +     case V4L2_BUF_TYPE_VIDEO_OUTPUT:
>> +             return &ctx->in;
>> +     case V4L2_BUF_TYPE_VIDEO_CAPTURE:
>> +             return &ctx->out;
>> +     default:
>> +             return ERR_PTR(-EINVAL);
>> +     }
>> +}
>> +
>> +static int rga_open(struct file *file)
>> +{
>> +     struct rockchip_rga *rga = video_drvdata(file);
>> +     struct rga_ctx *ctx = NULL;
>> +     int ret = 0;
>> +
>> +     ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
>> +     if (!ctx)
>> +             return -ENOMEM;
>> +     ctx->rga = rga;
>> +     /* Set default formats */
>> +     ctx->in = def_frame;
>> +     ctx->out = def_frame;
>> +
>> +     if (mutex_lock_interruptible(&rga->mutex)) {
>> +             kfree(ctx);
>> +             return -ERESTARTSYS;
>> +     }
>> +     ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
>> +     if (IS_ERR(ctx->fh.m2m_ctx)) {
>> +             ret = PTR_ERR(ctx->fh.m2m_ctx);
>> +             mutex_unlock(&rga->mutex);
>> +             kfree(ctx);
>> +             return ret;
>> +     }
>> +     v4l2_fh_init(&ctx->fh, video_devdata(file));
>> +     file->private_data = &ctx->fh;
>> +     v4l2_fh_add(&ctx->fh);
>> +
>> +     rga_setup_ctrls(ctx);
>> +
>> +     /* Write the default values to the ctx struct */
>> +     v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
>> +
>> +     ctx->fh.ctrl_handler = &ctx->ctrl_handler;
>> +     mutex_unlock(&rga->mutex);
>> +
>> +     return 0;
>> +}
>> +
>> +static int rga_release(struct file *file)
>> +{
>> +     struct rga_ctx *ctx =
>> +             container_of(file->private_data, struct rga_ctx, fh);
>> +     struct rockchip_rga *rga = ctx->rga;
>> +
>> +     mutex_lock(&rga->mutex);
>> +
>> +     v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
>> +
>> +     v4l2_ctrl_handler_free(&ctx->ctrl_handler);
>> +     v4l2_fh_del(&ctx->fh);
>> +     v4l2_fh_exit(&ctx->fh);
>> +     kfree(ctx);
>> +
>> +     mutex_unlock(&rga->mutex);
>> +
>> +     return 0;
>> +}
>> +
>> +static const struct v4l2_file_operations rga_fops = {
>> +     .owner = THIS_MODULE,
>> +     .open = rga_open,
>> +     .release = rga_release,
>> +     .poll = v4l2_m2m_fop_poll,
>> +     .unlocked_ioctl = video_ioctl2,
>> +     .mmap = v4l2_m2m_fop_mmap,
>> +};
>> +
>> +static int
>> +vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
>> +{
>> +     strlcpy(cap->driver, RGA_NAME, sizeof(cap->driver));
>> +     strlcpy(cap->card, "rockchip-rga", sizeof(cap->card));
>> +     strlcpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
>> +
>> +     return 0;
>> +}
>> +
>> +static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
>> +{
>> +     struct rga_fmt *fmt;
>> +
>> +     if (f->index >= NUM_FORMATS)
>> +             return -EINVAL;
>> +
>> +     fmt = &formats[f->index];
>> +     f->pixelformat = fmt->fourcc;
>> +
>> +     return 0;
>> +}
>> +
>> +static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
>> +{
>> +     struct rga_ctx *ctx = prv;
>> +     struct vb2_queue *vq;
>> +     struct rga_frame *frm;
>> +
>> +     vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
>> +     if (!vq)
>> +             return -EINVAL;
>> +     frm = rga_get_frame(ctx, f->type);
>> +     if (IS_ERR(frm))
>> +             return PTR_ERR(frm);
>> +
>> +     f->fmt.pix.width = frm->width;
>> +     f->fmt.pix.height = frm->height;
>> +     f->fmt.pix.field = V4L2_FIELD_NONE;
>> +     f->fmt.pix.pixelformat = frm->fmt->fourcc;
>> +     f->fmt.pix.bytesperline = frm->stride;
>> +     f->fmt.pix.sizeimage = frm->size;
>> +     f->fmt.pix.colorspace = frm->colorspace;
>> +
>> +     return 0;
>> +}
>> +
>> +static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
>> +{
>> +     struct rga_fmt *fmt;
>> +
>> +     fmt = rga_fmt_find(f);
>> +     if (!fmt) {
>> +             fmt = &formats[0];
>> +             f->fmt.pix.pixelformat = fmt->fourcc;
>> +     }
>> +
>> +     f->fmt.pix.field = V4L2_FIELD_NONE;
>> +
>> +     if (f->fmt.pix.width > MAX_WIDTH)
>> +             f->fmt.pix.width = MAX_WIDTH;
>> +     if (f->fmt.pix.height > MAX_HEIGHT)
>> +             f->fmt.pix.height = MAX_HEIGHT;
>> +
>> +     if (f->fmt.pix.width < MIN_WIDTH)
>> +             f->fmt.pix.width = MIN_WIDTH;
>> +     if (f->fmt.pix.height < MIN_HEIGHT)
>> +             f->fmt.pix.height = MIN_HEIGHT;
>> +
>> +     if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
>> +             f->fmt.pix.bytesperline = f->fmt.pix.width;
>> +     else
>> +             f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
>> +
>> +     f->fmt.pix.sizeimage =
>> +             f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
>> +
>> +     return 0;
>> +}
>> +
>> +static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
>> +{
>> +     struct rga_ctx *ctx = prv;
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     struct vb2_queue *vq;
>> +     struct rga_frame *frm;
>> +     struct rga_fmt *fmt;
>> +     int ret = 0;
>> +
>> +     /* Adjust all values accordingly to the hardware capabilities
>> +      * and chosen format.
>> +      */
>> +     ret = vidioc_try_fmt(file, prv, f);
>> +     if (ret)
>> +             return ret;
>> +     vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
>> +     if (vb2_is_busy(vq)) {
>> +             v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
>> +             return -EBUSY;
>> +     }
>> +     frm = rga_get_frame(ctx, f->type);
>> +     if (IS_ERR(frm))
>> +             return PTR_ERR(frm);
>> +     fmt = rga_fmt_find(f);
>> +     if (!fmt)
>> +             return -EINVAL;
>> +     frm->width = f->fmt.pix.width;
>> +     frm->height = f->fmt.pix.height;
>> +     frm->size = f->fmt.pix.sizeimage;
>> +     frm->fmt = fmt;
>> +     frm->stride = f->fmt.pix.bytesperline;
>> +     frm->colorspace = f->fmt.pix.colorspace;
>> +
>> +     /* Reset crop settings */
>> +     frm->crop.left = 0;
>> +     frm->crop.top = 0;
>> +     frm->crop.width = frm->width;
>> +     frm->crop.height = frm->height;
>> +
>> +     return 0;
>> +}
>> +
>> +static int
>> +vidioc_try_crop(struct rga_ctx *ctx, struct v4l2_selection *s)
>> +{
>> +     struct rockchip_rga *rga = ctx->rga;
>> +     struct rga_frame *f;
>> +
>> +     f = rga_get_frame(ctx, s->type);
>> +     if (IS_ERR(f))
>> +             return PTR_ERR(f);
>> +
>> +     switch (s->target) {
>> +     case V4L2_SEL_TGT_COMPOSE:
>> +             /*
>> +              * COMPOSE target is only valid for capture buffer type, return
>> +              * error for output buffer type
>> +              */
>> +             if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
>
> I think '!= V4L2_BUF_TYPE_VIDEO_CAPTURE' makes more sense.
>
>> +                     return -EINVAL;
>> +             break;
>> +     case V4L2_SEL_TGT_CROP:
>> +             /*
>> +              * CROP target is only valid for output buffer type, return
>> +              * error for capture buffer type
>> +              */
>> +             if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
>
> != V4L2_BUF_TYPE_VIDEO_OUTPUT
>
>> +                     return -EINVAL;
>> +             break;
>> +     /*
>> +      * bound and default crop/compose targets are invalid targets to
>> +      * try/set
>> +      */
>> +     default:
>> +             return -EINVAL;
>> +     }
>> +
>> +     if (s->r.top < 0 || s->r.left < 0) {
>> +             v4l2_err(&rga->v4l2_dev,
>> +                      "doesn't support negative values for top & left.\n");
>
> I'd make this v4l2_dbg.
>
>> +             return -EINVAL;
>> +     }
>> +
>> +     if (s->r.left + s->r.width > s->r.width ||
>> +         s->r.top + s->r.height > s->r.height ||
>
> Sorry, is this right? This basically means the same as:
>
> s->r.left != 0 || s->r.top != 0
>
> I suspect you want to test against the current v4l2_pix_format
> width and height since you compose into that buffer.
>
>> +         s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
>> +             v4l2_err(&rga->v4l2_dev, "unsupport crop value.\n");
>
> v4l2_dbg.
>
> s/unsupport/unsupported/
>
>> +             return -EINVAL;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static int vidioc_g_selection(struct file *file, void *prv,
>> +                           struct v4l2_selection *s)
>> +{
>> +     struct rga_ctx *ctx = prv;
>> +     struct rga_frame *f;
>> +     bool use_frame = false;
>> +
>> +     f = rga_get_frame(ctx, s->type);
>> +     if (IS_ERR(f))
>> +             return PTR_ERR(f);
>> +
>> +     switch (s->target) {
>> +     case V4L2_SEL_TGT_COMPOSE_DEFAULT:
>> +     case V4L2_SEL_TGT_COMPOSE_BOUNDS:
>> +             if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
>
> Same comment here, invert these conditions.
>
>> +                     return -EINVAL;
>> +             break;
>> +     case V4L2_SEL_TGT_CROP_BOUNDS:
>> +     case V4L2_SEL_TGT_CROP_DEFAULT:
>> +             if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
>> +                     return -EINVAL;
>> +             break;
>> +     case V4L2_SEL_TGT_COMPOSE:
>> +             if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
>> +                     return -EINVAL;
>> +             use_frame = true;
>> +             break;
>> +     case V4L2_SEL_TGT_CROP:
>> +             if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
>> +                     return -EINVAL;
>> +             use_frame = true;
>> +             break;
>> +     default:
>> +             return -EINVAL;
>> +     }
>> +
>> +     if (use_frame) {
>> +             s->r = f->crop;
>> +     } else {
>> +             s->r.left = 0;
>> +             s->r.top = 0;
>> +             s->r.width = f->width;
>> +             s->r.height = f->height;
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static int vidioc_s_selection(struct file *file, void *prv,
>> +                           struct v4l2_selection *s)
>> +{
>> +     struct rga_ctx *ctx = prv;
>> +     struct rga_frame *f;
>> +     int ret = 0;
>> +
>> +     ret = vidioc_try_crop(ctx, s);
>> +     if (ret)
>> +             return ret;
>> +
>> +     f = rga_get_frame(ctx, s->type);
>> +     if (IS_ERR(f))
>> +             return PTR_ERR(f);
>> +
>> +     f->crop = s->r;
>> +
>> +     return ret;
>> +}
>> +
>> +static const struct v4l2_ioctl_ops rga_ioctl_ops = {
>> +     .vidioc_querycap = vidioc_querycap,
>> +
>> +     .vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
>> +     .vidioc_g_fmt_vid_cap = vidioc_g_fmt,
>> +     .vidioc_try_fmt_vid_cap = vidioc_try_fmt,
>> +     .vidioc_s_fmt_vid_cap = vidioc_s_fmt,
>> +
>> +     .vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
>> +     .vidioc_g_fmt_vid_out = vidioc_g_fmt,
>> +     .vidioc_try_fmt_vid_out = vidioc_try_fmt,
>> +     .vidioc_s_fmt_vid_out = vidioc_s_fmt,
>> +
>> +     .vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
>> +     .vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
>> +     .vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
>> +     .vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
>> +     .vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
>> +     .vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
>> +     .vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
>> +
>> +     .vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
>> +     .vidioc_unsubscribe_event = v4l2_event_unsubscribe,
>> +
>> +     .vidioc_streamon = v4l2_m2m_ioctl_streamon,
>> +     .vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
>> +
>> +     .vidioc_g_selection = vidioc_g_selection,
>> +     .vidioc_s_selection = vidioc_s_selection,
>> +};
>> +
>> +static struct video_device rga_videodev = {
>> +     .name = "rockchip-rga",
>> +     .fops = &rga_fops,
>> +     .ioctl_ops = &rga_ioctl_ops,
>> +     .minor = -1,
>> +     .release = video_device_release,
>> +     .vfl_dir = VFL_DIR_M2M,
>> +     .device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
>> +};
>> +
>> +static int rga_enable_clocks(struct rockchip_rga *rga)
>> +{
>> +     int ret;
>> +
>> +     ret = clk_prepare_enable(rga->sclk);
>> +     if (ret) {
>> +             dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
>> +             return ret;
>> +     }
>> +
>> +     ret = clk_prepare_enable(rga->aclk);
>> +     if (ret) {
>> +             dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
>> +             goto err_disable_sclk;
>> +     }
>> +
>> +     ret = clk_prepare_enable(rga->hclk);
>> +     if (ret) {
>> +             dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
>> +             goto err_disable_aclk;
>> +     }
>> +
>> +     return 0;
>> +
>> +err_disable_sclk:
>> +     clk_disable_unprepare(rga->sclk);
>> +err_disable_aclk:
>> +     clk_disable_unprepare(rga->aclk);
>> +
>> +     return ret;
>> +}
>> +
>> +static void rga_disable_clocks(struct rockchip_rga *rga)
>> +{
>> +     clk_disable_unprepare(rga->sclk);
>> +     clk_disable_unprepare(rga->hclk);
>> +     clk_disable_unprepare(rga->aclk);
>> +}
>> +
>> +static int rga_parse_dt(struct rockchip_rga *rga)
>> +{
>> +     struct reset_control *core_rst, *axi_rst, *ahb_rst;
>> +
>> +     core_rst = devm_reset_control_get(rga->dev, "core");
>> +     if (IS_ERR(core_rst)) {
>> +             dev_err(rga->dev, "failed to get core reset controller\n");
>> +             return PTR_ERR(core_rst);
>> +     }
>> +
>> +     axi_rst = devm_reset_control_get(rga->dev, "axi");
>> +     if (IS_ERR(axi_rst)) {
>> +             dev_err(rga->dev, "failed to get axi reset controller\n");
>> +             return PTR_ERR(axi_rst);
>> +     }
>> +
>> +     ahb_rst = devm_reset_control_get(rga->dev, "ahb");
>> +     if (IS_ERR(ahb_rst)) {
>> +             dev_err(rga->dev, "failed to get ahb reset controller\n");
>> +             return PTR_ERR(ahb_rst);
>> +     }
>> +
>> +     reset_control_assert(core_rst);
>> +     udelay(1);
>> +     reset_control_deassert(core_rst);
>> +
>> +     reset_control_assert(axi_rst);
>> +     udelay(1);
>> +     reset_control_deassert(axi_rst);
>> +
>> +     reset_control_assert(ahb_rst);
>> +     udelay(1);
>> +     reset_control_deassert(ahb_rst);
>> +
>> +     rga->sclk = devm_clk_get(rga->dev, "sclk");
>> +     if (IS_ERR(rga->sclk)) {
>> +             dev_err(rga->dev, "failed to get sclk clock\n");
>> +             return PTR_ERR(rga->sclk);
>> +     }
>> +
>> +     rga->aclk = devm_clk_get(rga->dev, "aclk");
>> +     if (IS_ERR(rga->aclk)) {
>> +             dev_err(rga->dev, "failed to get aclk clock\n");
>> +             return PTR_ERR(rga->aclk);
>> +     }
>> +
>> +     rga->hclk = devm_clk_get(rga->dev, "hclk");
>> +     if (IS_ERR(rga->hclk)) {
>> +             dev_err(rga->dev, "failed to get hclk clock\n");
>> +             return PTR_ERR(rga->hclk);
>> +     }
>> +
>> +     return 0;
>> +}
>> +
>> +static int rga_probe(struct platform_device *pdev)
>> +{
>> +     struct rockchip_rga *rga;
>> +     struct video_device *vfd;
>> +     struct resource *res;
>> +     int ret = 0;
>> +     int irq;
>> +
>> +     if (!pdev->dev.of_node)
>> +             return -ENODEV;
>> +
>> +     rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
>> +     if (!rga)
>> +             return -ENOMEM;
>> +
>> +     rga->dev = &pdev->dev;
>> +     spin_lock_init(&rga->ctrl_lock);
>> +     mutex_init(&rga->mutex);
>> +
>> +     init_waitqueue_head(&rga->irq_queue);
>> +
>> +     ret = rga_parse_dt(rga);
>> +     if (ret)
>> +             dev_err(&pdev->dev, "Unable to parse OF data\n");
>> +
>> +     pm_runtime_enable(rga->dev);
>> +
>> +     res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
>> +
>> +     rga->regs = devm_ioremap_resource(rga->dev, res);
>> +     if (IS_ERR(rga->regs)) {
>> +             ret = PTR_ERR(rga->regs);
>> +             goto err_put_clk;
>> +     }
>> +
>> +     irq = platform_get_irq(pdev, 0);
>> +     if (irq < 0) {
>> +             dev_err(rga->dev, "failed to get irq\n");
>> +             ret = irq;
>> +             goto err_put_clk;
>> +     }
>> +
>> +     ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
>> +                            dev_name(rga->dev), rga);
>> +     if (ret < 0) {
>> +             dev_err(rga->dev, "failed to request irq\n");
>> +             goto err_put_clk;
>> +     }
>> +
>> +     ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
>> +     if (ret)
>> +             goto err_put_clk;
>> +     vfd = video_device_alloc();
>> +     if (!vfd) {
>> +             v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
>> +             ret = -ENOMEM;
>> +             goto unreg_v4l2_dev;
>> +     }
>> +     *vfd = rga_videodev;
>> +     vfd->lock = &rga->mutex;
>> +     vfd->v4l2_dev = &rga->v4l2_dev;
>> +
>> +     video_set_drvdata(vfd, rga);
>> +     snprintf(vfd->name, sizeof(vfd->name), "%s", rga_videodev.name);
>> +     rga->vfd = vfd;
>> +
>> +     platform_set_drvdata(pdev, rga);
>> +     rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
>> +     if (IS_ERR(rga->m2m_dev)) {
>> +             v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
>> +             ret = PTR_ERR(rga->m2m_dev);
>> +             goto unreg_video_dev;
>> +     }
>> +
>> +     pm_runtime_get_sync(rga->dev);
>> +
>> +     rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
>> +     rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
>> +
>> +     v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
>> +               rga->version.major, rga->version.minor);
>> +
>> +     pm_runtime_put(rga->dev);
>> +
>> +     /* Create CMD buffer */
>> +     rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
>> +                                        &rga->cmdbuf_phy, GFP_KERNEL,
>> +                                        DMA_ATTR_WRITE_COMBINE);
>> +
>> +     rga->src_mmu_pages =
>> +             (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
>> +     rga->dst_mmu_pages =
>> +             (unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
>> +
>> +     def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
>> +     def_frame.size = def_frame.stride * def_frame.height;
>> +
>> +     ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
>> +     if (ret) {
>> +             v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
>> +             goto rel_vdev;
>> +     }
>> +
>> +     v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
>> +               vfd->name, video_device_node_name(vfd));
>> +
>> +     return 0;
>> +
>> +rel_vdev:
>> +     video_device_release(vfd);
>> +unreg_video_dev:
>> +     video_unregister_device(rga->vfd);
>> +unreg_v4l2_dev:
>> +     v4l2_device_unregister(&rga->v4l2_dev);
>> +err_put_clk:
>> +     pm_runtime_disable(rga->dev);
>> +
>> +     return ret;
>> +}
>> +
>> +static int rga_remove(struct platform_device *pdev)
>> +{
>> +     struct rockchip_rga *rga = platform_get_drvdata(pdev);
>> +
>> +     dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, &rga->cmdbuf_virt,
>> +                    rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
>> +
>> +     free_pages((unsigned long)rga->src_mmu_pages, 3);
>> +     free_pages((unsigned long)rga->dst_mmu_pages, 3);
>> +
>> +     v4l2_info(&rga->v4l2_dev, "Removing\n");
>> +
>> +     v4l2_m2m_release(rga->m2m_dev);
>> +     video_unregister_device(rga->vfd);
>> +     v4l2_device_unregister(&rga->v4l2_dev);
>> +
>> +     pm_runtime_disable(rga->dev);
>> +
>> +     return 0;
>> +}
>> +
>> +#ifdef CONFIG_PM
>> +static int rga_runtime_suspend(struct device *dev)
>> +{
>> +     struct rockchip_rga *rga = dev_get_drvdata(dev);
>> +
>> +     rga_disable_clocks(rga);
>> +
>> +     return 0;
>> +}
>> +
>> +static int rga_runtime_resume(struct device *dev)
>> +{
>> +     struct rockchip_rga *rga = dev_get_drvdata(dev);
>> +
>> +     return rga_enable_clocks(rga);
>> +}
>> +#endif
>> +
>> +static const struct dev_pm_ops rga_pm = {
>> +     SET_RUNTIME_PM_OPS(rga_runtime_suspend,
>> +                        rga_runtime_resume, NULL)
>> +};
>> +
>> +static const struct of_device_id rockchip_rga_match[] = {
>> +     {
>> +             .compatible = "rockchip,rk3288-rga",
>> +     },
>> +     {
>> +             .compatible = "rockchip,rk3399-rga",
>> +     },
>> +     {},
>> +};
>> +
>> +MODULE_DEVICE_TABLE(of, rockchip_rga_match);
>> +
>> +static struct platform_driver rga_pdrv = {
>> +     .probe = rga_probe,
>> +     .remove = rga_remove,
>> +     .driver = {
>> +             .name = RGA_NAME,
>> +             .pm = &rga_pm,
>> +             .of_match_table = rockchip_rga_match,
>> +     },
>> +};
>> +
>> +module_platform_driver(rga_pdrv);
>> +
>> +MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
>> +MODULE_DESCRIPTION("Rockchip Raster 2d Grapphic Acceleration Unit");
>> +MODULE_LICENSE("GPL");
>> diff --git a/drivers/media/platform/rockchip-rga/rga.h b/drivers/media/platform/rockchip-rga/rga.h
>> new file mode 100644
>> index 0000000..c7d35b8
>> --- /dev/null
>> +++ b/drivers/media/platform/rockchip-rga/rga.h
>> @@ -0,0 +1,110 @@
>> +/*
>> + * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
>> + * Author: Jacob Chen <jacob-chen@iotwrt.com>
>> + *
>> + * This software is licensed under the terms of the GNU General Public
>> + * License version 2, as published by the Free Software Foundation, and
>> + * may be copied, distributed, and modified under those terms.
>> + *
>> + * This program is distributed in the hope that it will be useful,
>> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
>> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
>> + * GNU General Public License for more details.
>> + */
>> +#ifndef __RGA_H__
>> +#define __RGA_H__
>> +
>> +#include <linux/platform_device.h>
>> +#include <media/videobuf2-v4l2.h>
>> +#include <media/v4l2-ctrls.h>
>> +#include <media/v4l2-device.h>
>> +
>> +#define RGA_NAME "rockchip-rga"
>> +
>> +struct rga_fmt {
>> +     u32 fourcc;
>> +     int depth;
>> +     u8 uv_factor;
>> +     u8 y_div;
>> +     u8 x_div;
>> +     u8 color_swap;
>> +     u8 hw_format;
>> +};
>> +
>> +struct rga_frame {
>> +     /* Original dimensions */
>> +     u32 width;
>> +     u32 height;
>> +     u32 colorspace;
>> +
>> +     /* Crop */
>> +     struct v4l2_rect crop;
>> +
>> +     /* Image format */
>> +     struct rga_fmt *fmt;
>> +
>> +     /* Variables that can calculated once and reused */
>> +     u32 stride;
>> +     u32 size;
>> +};
>> +
>> +struct rockchip_rga_version {
>> +     u32 major;
>> +     u32 minor;
>> +};
>> +
>> +struct rga_ctx {
>> +     struct v4l2_fh fh;
>> +     struct rockchip_rga *rga;
>> +     struct rga_frame in;
>> +     struct rga_frame out;
>> +     struct v4l2_ctrl_handler ctrl_handler;
>> +
>> +     /* Control values */
>> +     u32 op;
>> +     u32 hflip;
>> +     u32 vflip;
>> +     u32 rotate;
>> +     u32 fill_color;
>> +};
>> +
>> +struct rockchip_rga {
>> +     struct v4l2_device v4l2_dev;
>> +     struct v4l2_m2m_dev *m2m_dev;
>> +     struct video_device *vfd;
>> +
>> +     struct device *dev;
>> +     struct regmap *grf;
>> +     void __iomem *regs;
>> +     struct clk *sclk;
>> +     struct clk *aclk;
>> +     struct clk *hclk;
>> +     struct rockchip_rga_version version;
>> +
>> +     struct mutex mutex;
>> +     spinlock_t ctrl_lock;
>> +
>> +     wait_queue_head_t irq_queue;
>> +
>> +     struct rga_ctx *curr;
>> +     dma_addr_t cmdbuf_phy;
>> +     void *cmdbuf_virt;
>> +     unsigned int *src_mmu_pages;
>> +     unsigned int *dst_mmu_pages;
>> +};
>> +
>> +struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type);
>> +
>> +/* RGA Buffers Manage Part */
>> +extern const struct vb2_ops rga_qops;
>> +void rga_buf_map(struct vb2_buffer *vb);
>> +
>> +/* RGA Hardware Part */
>> +void rga_write(struct rockchip_rga *rga, u32 reg, u32 value);
>> +u32 rga_read(struct rockchip_rga *rga, u32 reg);
>> +void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask);
>> +void rga_start(struct rockchip_rga *rga);
>> +
>> +void rga_cmd_set(struct rga_ctx *ctx);
>> +
>> +#endif
>>
>
> So this looks good, except for the fairly small comments above.
>
> As mentioned earlier, I need the v4l2-compliance output and I'll look at what is
> currently failing there. That should be fixed either in the driver or in the
> compliance test (if the problem is there).
>
> One other question: did you actually test crop/compose? Handling selection
> correctly is always tricky, so make sure this is tested.

I have test crop/compose, it work normally.

>
> Regards,
>
>         Hans
diff mbox

Patch

diff --git a/drivers/media/platform/Kconfig b/drivers/media/platform/Kconfig
index 041cb80a..d0d1a21 100644
--- a/drivers/media/platform/Kconfig
+++ b/drivers/media/platform/Kconfig
@@ -427,6 +427,17 @@  config VIDEO_RENESAS_VSP1
 	  To compile this driver as a module, choose M here: the module
 	  will be called vsp1.
 
+config VIDEO_ROCKCHIP_RGA
+	tristate "Rockchip Raster 2d Grapphic Acceleration Unit"
+	depends on VIDEO_DEV && VIDEO_V4L2 && HAS_DMA
+	depends on ARCH_ROCKCHIP || COMPILE_TEST
+	select VIDEOBUF2_DMA_SG
+	select V4L2_MEM2MEM_DEV
+	default n
+	---help---
+	  This is a v4l2 driver for Rockchip SOC RGA2
+	  2d graphics accelerator.
+
 config VIDEO_TI_VPE
 	tristate "TI VPE (Video Processing Engine) driver"
 	depends on VIDEO_DEV && VIDEO_V4L2
diff --git a/drivers/media/platform/Makefile b/drivers/media/platform/Makefile
index 63303d6..baf83060 100644
--- a/drivers/media/platform/Makefile
+++ b/drivers/media/platform/Makefile
@@ -57,6 +57,8 @@  obj-$(CONFIG_VIDEO_RENESAS_FDP1)	+= rcar_fdp1.o
 obj-$(CONFIG_VIDEO_RENESAS_JPU) 	+= rcar_jpu.o
 obj-$(CONFIG_VIDEO_RENESAS_VSP1)	+= vsp1/
 
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA)	+= rockchip-rga/
+
 obj-y	+= omap/
 
 obj-$(CONFIG_VIDEO_AM437X_VPFE)		+= am437x/
diff --git a/drivers/media/platform/rockchip-rga/Makefile b/drivers/media/platform/rockchip-rga/Makefile
new file mode 100644
index 0000000..92fe254
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/Makefile
@@ -0,0 +1,3 @@ 
+rockchip-rga-objs := rga.o rga-hw.o rga-buf.o
+
+obj-$(CONFIG_VIDEO_ROCKCHIP_RGA) += rockchip-rga.o
diff --git a/drivers/media/platform/rockchip-rga/rga-buf.c b/drivers/media/platform/rockchip-rga/rga-buf.c
new file mode 100644
index 0000000..6a9fd2c
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga-buf.c
@@ -0,0 +1,155 @@ 
+/*
+ * Copyright (C) 2017 Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen <jacob-chen@iotwrt.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/pm_runtime.h>
+
+#include <media/v4l2-device.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-dma-sg.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "rga-hw.h"
+#include "rga.h"
+
+static int
+rga_queue_setup(struct vb2_queue *vq,
+		unsigned int *nbuffers, unsigned int *nplanes,
+		unsigned int sizes[], struct device *alloc_devs[])
+{
+	struct rga_ctx *ctx = vb2_get_drv_priv(vq);
+	struct rga_frame *f = rga_get_frame(ctx, vq->type);
+
+	if (IS_ERR(f))
+		return PTR_ERR(f);
+
+	if (*nplanes)
+		return sizes[0] < f->size ? -EINVAL : 0;
+
+	sizes[0] = f->size;
+	*nplanes = 1;
+
+	return 0;
+}
+
+static int rga_buf_prepare(struct vb2_buffer *vb)
+{
+	struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct rga_frame *f = rga_get_frame(ctx, vb->vb2_queue->type);
+
+	if (IS_ERR(f))
+		return PTR_ERR(f);
+
+	vb2_set_plane_payload(vb, 0, f->size);
+
+	return 0;
+}
+
+static void rga_buf_queue(struct vb2_buffer *vb)
+{
+	struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
+	struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+
+	v4l2_m2m_buf_queue(ctx->fh.m2m_ctx, vbuf);
+}
+
+static int rga_buf_start_streaming(struct vb2_queue *q, unsigned int count)
+{
+	struct rga_ctx *ctx = vb2_get_drv_priv(q);
+	struct rockchip_rga *rga = ctx->rga;
+	int ret, i;
+
+	ret = pm_runtime_get_sync(rga->dev);
+
+	if (ret < 0) {
+		for (i = 0; i < q->num_buffers; ++i) {
+			if (q->bufs[i]->state == VB2_BUF_STATE_ACTIVE) {
+				v4l2_m2m_buf_done(to_vb2_v4l2_buffer(q->bufs[i]),
+						VB2_BUF_STATE_QUEUED);
+			}
+		}
+
+		return ret;
+	}
+
+	return 0;
+}
+
+static void rga_buf_stop_streaming(struct vb2_queue *q)
+{
+	struct rga_ctx *ctx = vb2_get_drv_priv(q);
+	struct rockchip_rga *rga = ctx->rga;
+	struct vb2_v4l2_buffer *vbuf;
+
+	for (;;) {
+		if (V4L2_TYPE_IS_OUTPUT(q->type))
+			vbuf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+		else
+			vbuf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+		if (!vbuf)
+			break;
+		v4l2_m2m_buf_done(vbuf, VB2_BUF_STATE_ERROR);
+	}
+
+	pm_runtime_put(rga->dev);
+}
+
+const struct vb2_ops rga_qops = {
+	.queue_setup = rga_queue_setup,
+	.buf_prepare = rga_buf_prepare,
+	.buf_queue = rga_buf_queue,
+	.wait_prepare = vb2_ops_wait_prepare,
+	.wait_finish = vb2_ops_wait_finish,
+	.start_streaming = rga_buf_start_streaming,
+	.stop_streaming = rga_buf_stop_streaming,
+};
+
+/* RGA MMU is a 1-Level MMU, so it can't be used through the IOMMU API.
+ * We use it more like a scatter-gather list.
+ */
+void rga_buf_map(struct vb2_buffer *vb)
+{
+	struct rga_ctx *ctx = vb2_get_drv_priv(vb->vb2_queue);
+	struct rockchip_rga *rga = ctx->rga;
+	struct sg_table *sgt;
+	struct scatterlist *sgl;
+	unsigned int *pages;
+	unsigned int address, len, i, p;
+	unsigned int mapped_size = 0;
+
+	if (vb->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+		pages = rga->src_mmu_pages;
+	else
+		pages = rga->dst_mmu_pages;
+
+	/* Create local MMU table for RGA */
+	sgt = vb2_plane_cookie(vb, 0);
+
+	for_each_sg(sgt->sgl, sgl, sgt->nents, i) {
+		len = sg_dma_len(sgl) >> PAGE_SHIFT;
+		address = sg_phys(sgl);
+
+		for (p = 0; p < len; p++) {
+			dma_addr_t phys = address + (p << PAGE_SHIFT);
+
+			pages[mapped_size + p] = phys;
+		}
+
+		mapped_size += len;
+	}
+
+	/* sync local MMU table for RGA */
+	dma_sync_single_for_device(rga->dev, virt_to_phys(pages),
+				   8 * PAGE_SIZE, DMA_BIDIRECTIONAL);
+}
diff --git a/drivers/media/platform/rockchip-rga/rga-hw.c b/drivers/media/platform/rockchip-rga/rga-hw.c
new file mode 100644
index 0000000..5b7ee58
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga-hw.c
@@ -0,0 +1,670 @@ 
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen <jacob-chen@iotwrt.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/pm_runtime.h>
+
+#include "rga-hw.h"
+#include "rga.h"
+
+enum e_rga_start_pos {
+	LT = 0,
+	LB = 1,
+	RT = 2,
+	RB = 3,
+};
+
+struct rga_addr_offset {
+	unsigned int y_off;
+	unsigned int u_off;
+	unsigned int v_off;
+};
+
+struct rga_corners_addr_offset {
+	struct rga_addr_offset left_top;
+	struct rga_addr_offset right_top;
+	struct rga_addr_offset left_bottom;
+	struct rga_addr_offset right_bottom;
+};
+
+static unsigned int rga_get_scaling(unsigned int src, unsigned int dst)
+{
+	/*
+	 * The rga hw scaling factor is a normalized inverse of the
+	 * scaling factor.
+	 * For example: When source width is 100 and destination width is 200
+	 * (scaling of 2x), then the hw factor is NC * 100 / 200.
+	 * The normalization factor (NC) is 2^16 = 0x10000.
+	 */
+
+	return (src > dst) ? ((dst << 16) / src) : ((src << 16) / dst);
+}
+
+static struct rga_corners_addr_offset
+rga_get_addr_offset(struct rga_frame *frm, unsigned int x, unsigned int y,
+		    unsigned int w, unsigned int h)
+{
+	struct rga_corners_addr_offset offsets;
+	struct rga_addr_offset *lt, *lb, *rt, *rb;
+	unsigned int x_div = 0,
+		     y_div = 0, uv_stride = 0, pixel_width = 0, uv_factor = 0;
+
+	lt = &offsets.left_top;
+	lb = &offsets.left_bottom;
+	rt = &offsets.right_top;
+	rb = &offsets.right_bottom;
+
+	x_div = frm->fmt->x_div;
+	y_div = frm->fmt->y_div;
+	uv_factor = frm->fmt->uv_factor;
+	uv_stride = frm->stride / x_div;
+	pixel_width = frm->stride / frm->width;
+
+	lt->y_off = y * frm->stride + x * pixel_width;
+	lt->u_off =
+		frm->width * frm->height + (y / y_div) * uv_stride + x / x_div;
+	lt->v_off = lt->u_off + frm->width * frm->height / uv_factor;
+
+	lb->y_off = lt->y_off + (h - 1) * frm->stride;
+	lb->u_off = lt->u_off + (h / y_div - 1) * uv_stride;
+	lb->v_off = lt->v_off + (h / y_div - 1) * uv_stride;
+
+	rt->y_off = lt->y_off + (w - 1) * pixel_width;
+	rt->u_off = lt->u_off + w / x_div - 1;
+	rt->v_off = lt->v_off + w / x_div - 1;
+
+	rb->y_off = lb->y_off + (w - 1) * pixel_width;
+	rb->u_off = lb->u_off + w / x_div - 1;
+	rb->v_off = lb->v_off + w / x_div - 1;
+
+	return offsets;
+}
+
+static struct rga_addr_offset *rga_lookup_draw_pos(struct
+		rga_corners_addr_offset
+		* offsets, u32 rotate_mode,
+		u32 mirr_mode)
+{
+	static enum e_rga_start_pos rot_mir_point_matrix[4][4] = {
+		{
+			LT, RT, LB, RB,
+		},
+		{
+			RT, LT, RB, LB,
+		},
+		{
+			RB, LB, RT, LT,
+		},
+		{
+			LB, RB, LT, RT,
+		},
+	};
+
+	if (!offsets)
+		return NULL;
+
+	switch (rot_mir_point_matrix[rotate_mode][mirr_mode]) {
+	case LT:
+		return &offsets->left_top;
+	case LB:
+		return &offsets->left_bottom;
+	case RT:
+		return &offsets->right_top;
+	case RB:
+		return &offsets->right_bottom;
+	}
+
+	return NULL;
+}
+
+static void rga_cmd_set_src_addr(struct rga_ctx *ctx, void *mmu_pages)
+{
+	struct rockchip_rga *rga = ctx->rga;
+	u32 *dest = rga->cmdbuf_virt;
+	unsigned int reg;
+
+	reg = RGA_MMU_SRC_BASE - RGA_MODE_BASE_REG;
+	dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
+
+	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
+	dest[reg >> 2] |= 0x7;
+}
+
+static void rga_cmd_set_src1_addr(struct rga_ctx *ctx, void *mmu_pages)
+{
+	struct rockchip_rga *rga = ctx->rga;
+	u32 *dest = rga->cmdbuf_virt;
+	unsigned int reg;
+
+	reg = RGA_MMU_SRC1_BASE - RGA_MODE_BASE_REG;
+	dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
+
+	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
+	dest[reg >> 2] |= 0x7 << 4;
+}
+
+static void rga_cmd_set_dst_addr(struct rga_ctx *ctx, void *mmu_pages)
+{
+	struct rockchip_rga *rga = ctx->rga;
+	u32 *dest = rga->cmdbuf_virt;
+	unsigned int reg;
+
+	reg = RGA_MMU_DST_BASE - RGA_MODE_BASE_REG;
+	dest[reg >> 2] = virt_to_phys(mmu_pages) >> 4;
+
+	reg = RGA_MMU_CTRL1 - RGA_MODE_BASE_REG;
+	dest[reg >> 2] |= 0x7 << 8;
+}
+
+static void rga_cmd_set_trans_info(struct rga_ctx *ctx)
+{
+	struct rockchip_rga *rga = ctx->rga;
+	u32 *dest = rga->cmdbuf_virt;
+	unsigned int scale_dst_w, scale_dst_h;
+	unsigned int src_h, src_w, src_x, src_y, dst_h, dst_w, dst_x, dst_y;
+	union rga_src_info src_info;
+	union rga_dst_info dst_info;
+	union rga_src_x_factor x_factor;
+	union rga_src_y_factor y_factor;
+	union rga_src_vir_info src_vir_info;
+	union rga_src_act_info src_act_info;
+	union rga_dst_vir_info dst_vir_info;
+	union rga_dst_act_info dst_act_info;
+
+	struct rga_addr_offset *dst_offset;
+	struct rga_corners_addr_offset offsets;
+	struct rga_corners_addr_offset src_offsets;
+
+	src_h = ctx->in.crop.height;
+	src_w = ctx->in.crop.width;
+	src_x = ctx->in.crop.left;
+	src_y = ctx->in.crop.top;
+	dst_h = ctx->out.crop.height;
+	dst_w = ctx->out.crop.width;
+	dst_x = ctx->out.crop.left;
+	dst_y = ctx->out.crop.top;
+
+	src_info.val = dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2];
+	dst_info.val = dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2];
+	x_factor.val = dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2];
+	y_factor.val = dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2];
+	src_vir_info.val = dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
+	src_act_info.val = dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
+	dst_vir_info.val = dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2];
+	dst_act_info.val = dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2];
+
+	src_info.data.format = ctx->in.fmt->hw_format;
+	src_info.data.swap = ctx->in.fmt->color_swap;
+	dst_info.data.format = ctx->out.fmt->hw_format;
+	dst_info.data.swap = ctx->out.fmt->color_swap;
+
+	if (ctx->in.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
+		if (ctx->out.fmt->hw_format < RGA_COLOR_FMT_YUV422SP) {
+			switch (ctx->in.colorspace) {
+			case V4L2_COLORSPACE_REC709:
+				src_info.data.csc_mode =
+					RGA_SRC_CSC_MODE_BT709_R0;
+				break;
+			default:
+				src_info.data.csc_mode =
+					RGA_SRC_CSC_MODE_BT601_R0;
+				break;
+			}
+		}
+	}
+
+	if (ctx->out.fmt->hw_format >= RGA_COLOR_FMT_YUV422SP) {
+		switch (ctx->out.colorspace) {
+		case V4L2_COLORSPACE_REC709:
+			dst_info.data.csc_mode = RGA_SRC_CSC_MODE_BT709_R0;
+			break;
+		default:
+			dst_info.data.csc_mode = RGA_DST_CSC_MODE_BT601_R0;
+			break;
+		}
+	}
+
+	if (ctx->op == V4L2_PORTER_DUFF_CLEAR) {
+		/*
+		 * Configure the target color to foreground color.
+		 */
+		dest[(RGA_SRC_FG_COLOR - RGA_MODE_BASE_REG) >> 2] =
+			ctx->fill_color;
+		dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
+		dst_act_info.data.act_height = dst_h - 1;
+		dst_act_info.data.act_width = dst_w - 1;
+
+		offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y,
+					      dst_w, dst_h);
+		dst_offset = &offsets.left_top;
+
+		goto write_dst;
+	}
+
+	if (ctx->vflip)
+		src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_X;
+
+	if (ctx->hflip)
+		src_info.data.mir_mode |= RGA_SRC_MIRR_MODE_Y;
+
+	switch (ctx->rotate) {
+	case 90:
+		src_info.data.rot_mode = RGA_SRC_ROT_MODE_90_DEGREE;
+		break;
+	case 180:
+		src_info.data.rot_mode = RGA_SRC_ROT_MODE_180_DEGREE;
+		break;
+	case 270:
+		src_info.data.rot_mode = RGA_SRC_ROT_MODE_270_DEGREE;
+		break;
+	default:
+		src_info.data.rot_mode = RGA_SRC_ROT_MODE_0_DEGREE;
+		break;
+	}
+
+	/*
+	 * Cacluate the up/down scaling mode/factor.
+	 *
+	 * RGA used to scale the picture first, and then rotate second,
+	 * so we need to swap the w/h when rotate degree is 90/270.
+	 */
+	if (src_info.data.rot_mode == RGA_SRC_ROT_MODE_90_DEGREE ||
+	    src_info.data.rot_mode == RGA_SRC_ROT_MODE_270_DEGREE) {
+		if (rga->version.major == 0 || rga->version.minor == 0) {
+			if (dst_w == src_h)
+				src_h -= 8;
+			if (abs(src_w - dst_h) < 16)
+				src_w -= 16;
+		}
+
+		scale_dst_h = dst_w;
+		scale_dst_w = dst_h;
+	} else {
+		scale_dst_w = dst_w;
+		scale_dst_h = dst_h;
+	}
+
+	if (src_w == scale_dst_w) {
+		src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_NO;
+		x_factor.val = 0;
+	} else if (src_w > scale_dst_w) {
+		src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_DOWN;
+		x_factor.data.down_scale_factor =
+			rga_get_scaling(src_w, scale_dst_w) + 1;
+	} else {
+		src_info.data.hscl_mode = RGA_SRC_HSCL_MODE_UP;
+		x_factor.data.up_scale_factor =
+			rga_get_scaling(src_w - 1, scale_dst_w - 1);
+	}
+
+	if (src_h == scale_dst_h) {
+		src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_NO;
+		y_factor.val = 0;
+	} else if (src_h > scale_dst_h) {
+		src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_DOWN;
+		y_factor.data.down_scale_factor =
+			rga_get_scaling(src_h, scale_dst_h) + 1;
+	} else {
+		src_info.data.vscl_mode = RGA_SRC_VSCL_MODE_UP;
+		y_factor.data.up_scale_factor =
+			rga_get_scaling(src_h - 1, scale_dst_h - 1);
+	}
+
+	/*
+	 * Cacluate the framebuffer virtual strides and active size,
+	 * note that the step of vir_stride / vir_width is 4 byte words
+	 */
+	src_vir_info.data.vir_stride = ctx->in.stride >> 2;
+	src_vir_info.data.vir_width = ctx->in.stride >> 2;
+
+	src_act_info.data.act_height = src_h - 1;
+	src_act_info.data.act_width = src_w - 1;
+
+	dst_vir_info.data.vir_stride = ctx->out.stride >> 2;
+	dst_act_info.data.act_height = dst_h - 1;
+	dst_act_info.data.act_width = dst_w - 1;
+
+	/*
+	 * Cacluate the source framebuffer base address with offset pixel.
+	 */
+	src_offsets = rga_get_addr_offset(&ctx->in, src_x, src_y,
+					  src_w, src_h);
+
+	/*
+	 * Configure the dest framebuffer base address with pixel offset.
+	 */
+	offsets = rga_get_addr_offset(&ctx->out, dst_x, dst_y, dst_w, dst_h);
+	dst_offset = rga_lookup_draw_pos(&offsets, src_info.data.rot_mode,
+					 src_info.data.mir_mode);
+
+	dest[(RGA_SRC_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
+		src_offsets.left_top.y_off;
+	dest[(RGA_SRC_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
+		src_offsets.left_top.u_off;
+	dest[(RGA_SRC_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
+		src_offsets.left_top.v_off;
+
+	dest[(RGA_SRC_X_FACTOR - RGA_MODE_BASE_REG) >> 2] = x_factor.val;
+	dest[(RGA_SRC_Y_FACTOR - RGA_MODE_BASE_REG) >> 2] = y_factor.val;
+	dest[(RGA_SRC_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = src_vir_info.val;
+	dest[(RGA_SRC_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = src_act_info.val;
+
+	dest[(RGA_SRC_INFO - RGA_MODE_BASE_REG) >> 2] = src_info.val;
+
+write_dst:
+	dest[(RGA_DST_Y_RGB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
+		dst_offset->y_off;
+	dest[(RGA_DST_CB_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
+		dst_offset->u_off;
+	dest[(RGA_DST_CR_BASE_ADDR - RGA_MODE_BASE_REG) >> 2] =
+		dst_offset->v_off;
+
+	dest[(RGA_DST_VIR_INFO - RGA_MODE_BASE_REG) >> 2] = dst_vir_info.val;
+	dest[(RGA_DST_ACT_INFO - RGA_MODE_BASE_REG) >> 2] = dst_act_info.val;
+
+	dest[(RGA_DST_INFO - RGA_MODE_BASE_REG) >> 2] = dst_info.val;
+}
+
+static void rga_cmd_set_mode(struct rga_ctx *ctx)
+{
+	struct rockchip_rga *rga = ctx->rga;
+	u32 *dest = rga->cmdbuf_virt;
+	union rga_mode_ctrl mode;
+	union rga_alpha_ctrl0 alpha_ctrl0;
+	union rga_alpha_ctrl1 alpha_ctrl1;
+
+	mode.val = 0;
+	alpha_ctrl0.val = 0;
+	alpha_ctrl1.val = 0;
+
+	switch (ctx->op) {
+	case V4L2_PORTER_DUFF_CLEAR:
+		mode.data.gradient_sat = 1;
+		mode.data.render = RGA_MODE_RENDER_RECTANGLE_FILL;
+		mode.data.cf_rop4_pat = RGA_MODE_CF_ROP4_SOLID;
+		mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
+		break;
+	case V4L2_PORTER_DUFF_DST:
+	case V4L2_PORTER_DUFF_DSTATOP:
+	case V4L2_PORTER_DUFF_DSTIN:
+	case V4L2_PORTER_DUFF_DSTOUT:
+	case V4L2_PORTER_DUFF_DSTOVER:
+	case V4L2_PORTER_DUFF_SRCATOP:
+	case V4L2_PORTER_DUFF_SRCIN:
+	case V4L2_PORTER_DUFF_SRCOUT:
+	case V4L2_PORTER_DUFF_SRCOVER:
+		mode.data.gradient_sat = 1;
+		mode.data.render = RGA_MODE_RENDER_BITBLT;
+		mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
+
+		alpha_ctrl0.data.rop_en = 1;
+		alpha_ctrl0.data.rop_mode = RGA_ALPHA_ROP_MODE_3;
+		alpha_ctrl0.data.rop_select = RGA_ALPHA_SELECT_ALPHA;
+
+		alpha_ctrl1.data.dst_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
+		alpha_ctrl1.data.src_alpha_cal_m0 = RGA_ALPHA_CAL_NORMAL;
+		alpha_ctrl1.data.dst_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
+		alpha_ctrl1.data.src_alpha_cal_m1 = RGA_ALPHA_CAL_NORMAL;
+		break;
+	default:
+		mode.data.gradient_sat = 1;
+		mode.data.render = RGA_MODE_RENDER_BITBLT;
+		mode.data.bitblt = RGA_MODE_BITBLT_MODE_SRC_TO_DST;
+		break;
+	}
+
+	switch (ctx->op) {
+	case V4L2_PORTER_DUFF_DST:
+		/* A=Dst.a */
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
+
+		/* C=Dst.c */
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
+		break;
+	case V4L2_PORTER_DUFF_DSTATOP:
+		/* A=Src.a */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
+
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		/* C=Src.a*Dst.c+Src.c*(1.0-Dst.a) */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
+		break;
+	case V4L2_PORTER_DUFF_DSTIN:
+		/* A=Dst.a*Src.a */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
+
+		/* C=Dst.c*Src.a */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
+		break;
+	case V4L2_PORTER_DUFF_DSTOUT:
+		/* A=Dst.a*(1.0-Src.a) */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		/* C=Dst.c*(1.0-Src.a) */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+		break;
+	case V4L2_PORTER_DUFF_DSTOVER:
+		/* A=Src.a+Dst.a*(1.0-Src.a) */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		/* C=Dst.c+Src.c*(1.0-Dst.a) */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ONE;
+		break;
+	case V4L2_PORTER_DUFF_SRCATOP:
+		/* A=Dst.a */
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ONE;
+
+		/* C=Dst.a*Src.c+Dst.c*(1.0-Src.a) */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+		break;
+	case V4L2_PORTER_DUFF_SRCIN:
+		/* A=Src.a*Dst.a */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER;
+
+		/* C=Src.c*Dst.a */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
+		break;
+	case V4L2_PORTER_DUFF_SRCOUT:
+		/* A=Src.a*(1.0-Dst.a) */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_ZERO;
+
+		/* C=Src.c*(1.0-Dst.a) */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_ZERO;
+		break;
+	case V4L2_PORTER_DUFF_SRCOVER:
+		/* A=Src.a+Dst.a*(1.0-Src.a) */
+		alpha_ctrl1.data.src_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m1 = RGA_ALPHA_FACTOR_ONE;
+
+		alpha_ctrl1.data.dst_alpha_m1 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m1 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m1 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+
+		/* C=Src.c+Dst.c*(1.0-Src.a) */
+		alpha_ctrl1.data.src_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.src_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.src_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.src_factor_m0 = RGA_ALPHA_FACTOR_ONE;
+
+		alpha_ctrl1.data.dst_color_m0 = RGA_ALPHA_COLOR_NORMAL;
+		alpha_ctrl1.data.dst_alpha_m0 = RGA_ALPHA_NORMAL;
+		alpha_ctrl1.data.dst_blend_m0 = RGA_ALPHA_BLEND_NORMAL;
+		alpha_ctrl1.data.dst_factor_m0 = RGA_ALPHA_FACTOR_OTHER_REVERSE;
+		break;
+	default:
+		break;
+	}
+
+	dest[(RGA_ALPHA_CTRL0 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl0.val;
+	dest[(RGA_ALPHA_CTRL1 - RGA_MODE_BASE_REG) >> 2] = alpha_ctrl1.val;
+
+	dest[(RGA_MODE_CTRL - RGA_MODE_BASE_REG) >> 2] = mode.val;
+}
+
+void rga_cmd_set(struct rga_ctx *ctx)
+{
+	struct rockchip_rga *rga = ctx->rga;
+
+	memset(rga->cmdbuf_virt, 0, RGA_CMDBUF_SIZE * 4);
+
+	if (ctx->op != V4L2_PORTER_DUFF_CLEAR) {
+		rga_cmd_set_src_addr(ctx, rga->src_mmu_pages);
+		/*
+		 * Due to hardware bug,
+		 * src1 mmu also should be configured when using alpha blending.
+		 */
+		rga_cmd_set_src1_addr(ctx, rga->dst_mmu_pages);
+	}
+	rga_cmd_set_dst_addr(ctx, rga->dst_mmu_pages);
+	rga_cmd_set_mode(ctx);
+
+	rga_cmd_set_trans_info(ctx);
+
+	rga_write(rga, RGA_CMD_BASE, rga->cmdbuf_phy);
+}
+
+void rga_write(struct rockchip_rga *rga, u32 reg, u32 value)
+{
+	writel(value, rga->regs + reg);
+}
+
+u32 rga_read(struct rockchip_rga *rga, u32 reg)
+{
+	return readl(rga->regs + reg);
+}
+
+void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask)
+{
+	u32 temp = rga_read(rga, reg) & ~(mask);
+
+	temp |= val & mask;
+	rga_write(rga, reg, temp);
+}
+
+void rga_start(struct rockchip_rga *rga)
+{
+	/* sync CMD buf for RGA */
+	dma_sync_single_for_device(rga->dev, rga->cmdbuf_phy,
+				   PAGE_SIZE, DMA_BIDIRECTIONAL);
+
+	rga_write(rga, RGA_SYS_CTRL, 0x00);
+
+	rga_write(rga, RGA_SYS_CTRL, 0x22);
+
+	rga_write(rga, RGA_INT, 0x600);
+
+	rga_write(rga, RGA_CMD_CTRL, 0x1);
+}
diff --git a/drivers/media/platform/rockchip-rga/rga-hw.h b/drivers/media/platform/rockchip-rga/rga-hw.h
new file mode 100644
index 0000000..a8b6353
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga-hw.h
@@ -0,0 +1,437 @@ 
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen <jacob-chen@iotwrt.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __RGA_HW_H__
+#define __RGA_HW_H__
+
+#define RGA_CMDBUF_SIZE 0x20
+
+/* Hardware limits */
+#define MAX_WIDTH 8192
+#define MAX_HEIGHT 8192
+
+#define MIN_WIDTH 34
+#define MIN_HEIGHT 34
+
+#define DEFAULT_WIDTH 100
+#define DEFAULT_HEIGHT 100
+
+#define RGA_TIMEOUT 500
+
+/* Registers address */
+#define RGA_SYS_CTRL 0x0000
+#define RGA_CMD_CTRL 0x0004
+#define RGA_CMD_BASE 0x0008
+#define RGA_INT 0x0010
+#define RGA_MMU_CTRL0 0x0014
+#define RGA_VERSION_INFO 0x0028
+
+#define RGA_MODE_BASE_REG 0x0100
+#define RGA_MODE_MAX_REG 0x017C
+
+#define RGA_MODE_CTRL 0x0100
+#define RGA_SRC_INFO 0x0104
+#define RGA_SRC_Y_RGB_BASE_ADDR 0x0108
+#define RGA_SRC_CB_BASE_ADDR 0x010c
+#define RGA_SRC_CR_BASE_ADDR 0x0110
+#define RGA_SRC1_RGB_BASE_ADDR 0x0114
+#define RGA_SRC_VIR_INFO 0x0118
+#define RGA_SRC_ACT_INFO 0x011c
+#define RGA_SRC_X_FACTOR 0x0120
+#define RGA_SRC_Y_FACTOR 0x0124
+#define RGA_SRC_BG_COLOR 0x0128
+#define RGA_SRC_FG_COLOR 0x012c
+#define RGA_SRC_TR_COLOR0 0x0130
+#define RGA_SRC_TR_COLOR1 0x0134
+
+#define RGA_DST_INFO 0x0138
+#define RGA_DST_Y_RGB_BASE_ADDR 0x013c
+#define RGA_DST_CB_BASE_ADDR 0x0140
+#define RGA_DST_CR_BASE_ADDR 0x0144
+#define RGA_DST_VIR_INFO 0x0148
+#define RGA_DST_ACT_INFO 0x014c
+
+#define RGA_ALPHA_CTRL0 0x0150
+#define RGA_ALPHA_CTRL1 0x0154
+#define RGA_FADING_CTRL 0x0158
+#define RGA_PAT_CON 0x015c
+#define RGA_ROP_CON0 0x0160
+#define RGA_ROP_CON1 0x0164
+#define RGA_MASK_BASE 0x0168
+
+#define RGA_MMU_CTRL1 0x016C
+#define RGA_MMU_SRC_BASE 0x0170
+#define RGA_MMU_SRC1_BASE 0x0174
+#define RGA_MMU_DST_BASE 0x0178
+
+/* Registers value */
+#define RGA_MODE_RENDER_BITBLT 0
+#define RGA_MODE_RENDER_COLOR_PALETTE 1
+#define RGA_MODE_RENDER_RECTANGLE_FILL 2
+#define RGA_MODE_RENDER_UPDATE_PALETTE_LUT_RAM 3
+
+#define RGA_MODE_BITBLT_MODE_SRC_TO_DST 0
+#define RGA_MODE_BITBLT_MODE_SRC_SRC1_TO_DST 1
+
+#define RGA_MODE_CF_ROP4_SOLID 0
+#define RGA_MODE_CF_ROP4_PATTERN 1
+
+#define RGA_COLOR_FMT_ABGR8888 0
+#define RGA_COLOR_FMT_XBGR8888 1
+#define RGA_COLOR_FMT_BGR888 2
+#define RGA_COLOR_FMT_BGR565 4
+#define RGA_COLOR_FMT_ABGR1555 5
+#define RGA_COLOR_FMT_ABGR4444 6
+#define RGA_COLOR_FMT_YUV422SP 8
+#define RGA_COLOR_FMT_YUV422P 9
+#define RGA_COLOR_FMT_YUV420SP 10
+#define RGA_COLOR_FMT_YUV420P 11
+/* SRC_COLOR Palette */
+#define RGA_COLOR_FMT_CP_1BPP 12
+#define RGA_COLOR_FMT_CP_2BPP 13
+#define RGA_COLOR_FMT_CP_4BPP 14
+#define RGA_COLOR_FMT_CP_8BPP 15
+#define RGA_COLOR_FMT_MASK 15
+
+#define RGA_COLOR_NONE_SWAP 0
+#define RGA_COLOR_RB_SWAP 1
+#define RGA_COLOR_ALPHA_SWAP 2
+#define RGA_COLOR_UV_SWAP 4
+
+#define RGA_SRC_CSC_MODE_BYPASS 0
+#define RGA_SRC_CSC_MODE_BT601_R0 1
+#define RGA_SRC_CSC_MODE_BT601_R1 2
+#define RGA_SRC_CSC_MODE_BT709_R0 3
+#define RGA_SRC_CSC_MODE_BT709_R1 4
+
+#define RGA_SRC_ROT_MODE_0_DEGREE 0
+#define RGA_SRC_ROT_MODE_90_DEGREE 1
+#define RGA_SRC_ROT_MODE_180_DEGREE 2
+#define RGA_SRC_ROT_MODE_270_DEGREE 3
+
+#define RGA_SRC_MIRR_MODE_NO 0
+#define RGA_SRC_MIRR_MODE_X 1
+#define RGA_SRC_MIRR_MODE_Y 2
+#define RGA_SRC_MIRR_MODE_X_Y 3
+
+#define RGA_SRC_HSCL_MODE_NO 0
+#define RGA_SRC_HSCL_MODE_DOWN 1
+#define RGA_SRC_HSCL_MODE_UP 2
+
+#define RGA_SRC_VSCL_MODE_NO 0
+#define RGA_SRC_VSCL_MODE_DOWN 1
+#define RGA_SRC_VSCL_MODE_UP 2
+
+#define RGA_SRC_TRANS_ENABLE_R 1
+#define RGA_SRC_TRANS_ENABLE_G 2
+#define RGA_SRC_TRANS_ENABLE_B 4
+#define RGA_SRC_TRANS_ENABLE_A 8
+
+#define RGA_SRC_BIC_COE_SELEC_CATROM 0
+#define RGA_SRC_BIC_COE_SELEC_MITCHELL 1
+#define RGA_SRC_BIC_COE_SELEC_HERMITE 2
+#define RGA_SRC_BIC_COE_SELEC_BSPLINE 3
+
+#define RGA_DST_DITHER_MODE_888_TO_666 0
+#define RGA_DST_DITHER_MODE_888_TO_565 1
+#define RGA_DST_DITHER_MODE_888_TO_555 2
+#define RGA_DST_DITHER_MODE_888_TO_444 3
+
+#define RGA_DST_CSC_MODE_BYPASS 0
+#define RGA_DST_CSC_MODE_BT601_R0 1
+#define RGA_DST_CSC_MODE_BT601_R1 2
+#define RGA_DST_CSC_MODE_BT709_R0 3
+
+#define RGA_ALPHA_ROP_MODE_2 0
+#define RGA_ALPHA_ROP_MODE_3 1
+#define RGA_ALPHA_ROP_MODE_4 2
+
+#define RGA_ALPHA_SELECT_ALPHA 0
+#define RGA_ALPHA_SELECT_ROP 1
+
+#define RGA_ALPHA_MASK_BIG_ENDIAN 0
+#define RGA_ALPHA_MASK_LITTLE_ENDIAN 1
+
+#define RGA_ALPHA_NORMAL 0
+#define RGA_ALPHA_REVERSE 1
+
+#define RGA_ALPHA_BLEND_GLOBAL 0
+#define RGA_ALPHA_BLEND_NORMAL 1
+#define RGA_ALPHA_BLEND_MULTIPLY 2
+
+#define RGA_ALPHA_CAL_CUT 0
+#define RGA_ALPHA_CAL_NORMAL 1
+
+#define RGA_ALPHA_FACTOR_ZERO 0
+#define RGA_ALPHA_FACTOR_ONE 1
+#define RGA_ALPHA_FACTOR_OTHER 2
+#define RGA_ALPHA_FACTOR_OTHER_REVERSE 3
+#define RGA_ALPHA_FACTOR_SELF 4
+
+#define RGA_ALPHA_COLOR_NORMAL 0
+#define RGA_ALPHA_COLOR_MULTIPLY_CAL 1
+
+/* Registers union */
+union rga_mode_ctrl {
+	unsigned int val;
+	struct {
+		/* [0:2] */
+		unsigned int render:3;
+		/* [3:6] */
+		unsigned int bitblt:1;
+		unsigned int cf_rop4_pat:1;
+		unsigned int alpha_zero_key:1;
+		unsigned int gradient_sat:1;
+		/* [7:31] */
+		unsigned int reserved:25;
+	} data;
+};
+
+union rga_src_info {
+	unsigned int val;
+	struct {
+		/* [0:3] */
+		unsigned int format:4;
+		/* [4:7] */
+		unsigned int swap:3;
+		unsigned int cp_endian:1;
+		/* [8:17] */
+		unsigned int csc_mode:2;
+		unsigned int rot_mode:2;
+		unsigned int mir_mode:2;
+		unsigned int hscl_mode:2;
+		unsigned int vscl_mode:2;
+		/* [18:22] */
+		unsigned int trans_mode:1;
+		unsigned int trans_enable:4;
+		/* [23:25] */
+		unsigned int dither_up_en:1;
+		unsigned int bic_coe_sel:2;
+		/* [26:31] */
+		unsigned int reserved:6;
+	} data;
+};
+
+union rga_src_vir_info {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int vir_width:15;
+		unsigned int reserved:1;
+		/* [16:25] */
+		unsigned int vir_stride:10;
+		/* [26:31] */
+		unsigned int reserved1:6;
+	} data;
+};
+
+union rga_src_act_info {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int act_width:13;
+		unsigned int reserved:3;
+		/* [16:31] */
+		unsigned int act_height:13;
+		unsigned int reserved1:3;
+	} data;
+};
+
+union rga_src_x_factor {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int down_scale_factor:16;
+		/* [16:31] */
+		unsigned int up_scale_factor:16;
+	} data;
+};
+
+union rga_src_y_factor {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int down_scale_factor:16;
+		/* [16:31] */
+		unsigned int up_scale_factor:16;
+	} data;
+};
+
+/* Alpha / Red / Green / Blue */
+union rga_src_cp_gr_color {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int gradient_x:16;
+		/* [16:31] */
+		unsigned int gradient_y:16;
+	} data;
+};
+
+union rga_src_transparency_color0 {
+	unsigned int val;
+	struct {
+		/* [0:7] */
+		unsigned int trans_rmin:8;
+		/* [8:15] */
+		unsigned int trans_gmin:8;
+		/* [16:23] */
+		unsigned int trans_bmin:8;
+		/* [24:31] */
+		unsigned int trans_amin:8;
+	} data;
+};
+
+union rga_src_transparency_color1 {
+	unsigned int val;
+	struct {
+		/* [0:7] */
+		unsigned int trans_rmax:8;
+		/* [8:15] */
+		unsigned int trans_gmax:8;
+		/* [16:23] */
+		unsigned int trans_bmax:8;
+		/* [24:31] */
+		unsigned int trans_amax:8;
+	} data;
+};
+
+union rga_dst_info {
+	unsigned int val;
+	struct {
+		/* [0:3] */
+		unsigned int format:4;
+		/* [4:6] */
+		unsigned int swap:3;
+		/* [7:9] */
+		unsigned int src1_format:3;
+		/* [10:11] */
+		unsigned int src1_swap:2;
+		/* [12:15] */
+		unsigned int dither_up_en:1;
+		unsigned int dither_down_en:1;
+		unsigned int dither_down_mode:2;
+		/* [16:18] */
+		unsigned int csc_mode:2;
+		unsigned int csc_clip:1;
+		/* [19:31] */
+		unsigned int reserved:13;
+	} data;
+};
+
+union rga_dst_vir_info {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int vir_stride:15;
+		unsigned int reserved:1;
+		/* [16:31] */
+		unsigned int src1_vir_stride:15;
+		unsigned int reserved1:1;
+	} data;
+};
+
+union rga_dst_act_info {
+	unsigned int val;
+	struct {
+		/* [0:15] */
+		unsigned int act_width:12;
+		unsigned int reserved:4;
+		/* [16:31] */
+		unsigned int act_height:12;
+		unsigned int reserved1:4;
+	} data;
+};
+
+union rga_alpha_ctrl0 {
+	unsigned int val;
+	struct {
+		/* [0:3] */
+		unsigned int rop_en:1;
+		unsigned int rop_select:1;
+		unsigned int rop_mode:2;
+		/* [4:11] */
+		unsigned int src_fading_val:8;
+		/* [12:20] */
+		unsigned int dst_fading_val:8;
+		unsigned int mask_endian:1;
+		/* [21:31] */
+		unsigned int reserved:11;
+	} data;
+};
+
+union rga_alpha_ctrl1 {
+	unsigned int val;
+	struct {
+		/* [0:1] */
+		unsigned int dst_color_m0:1;
+		unsigned int src_color_m0:1;
+		/* [2:7] */
+		unsigned int dst_factor_m0:3;
+		unsigned int src_factor_m0:3;
+		/* [8:9] */
+		unsigned int dst_alpha_cal_m0:1;
+		unsigned int src_alpha_cal_m0:1;
+		/* [10:13] */
+		unsigned int dst_blend_m0:2;
+		unsigned int src_blend_m0:2;
+		/* [14:15] */
+		unsigned int dst_alpha_m0:1;
+		unsigned int src_alpha_m0:1;
+		/* [16:21] */
+		unsigned int dst_factor_m1:3;
+		unsigned int src_factor_m1:3;
+		/* [22:23] */
+		unsigned int dst_alpha_cal_m1:1;
+		unsigned int src_alpha_cal_m1:1;
+		/* [24:27] */
+		unsigned int dst_blend_m1:2;
+		unsigned int src_blend_m1:2;
+		/* [28:29] */
+		unsigned int dst_alpha_m1:1;
+		unsigned int src_alpha_m1:1;
+		/* [30:31] */
+		unsigned int reserved:2;
+	} data;
+};
+
+union rga_fading_ctrl {
+	unsigned int val;
+	struct {
+		/* [0:7] */
+		unsigned int fading_offset_r:8;
+		/* [8:15] */
+		unsigned int fading_offset_g:8;
+		/* [16:23] */
+		unsigned int fading_offset_b:8;
+		/* [24:31] */
+		unsigned int fading_en:1;
+		unsigned int reserved:7;
+	} data;
+};
+
+union rga_pat_con {
+	unsigned int val;
+	struct {
+		/* [0:7] */
+		unsigned int width:8;
+		/* [8:15] */
+		unsigned int height:8;
+		/* [16:23] */
+		unsigned int offset_x:8;
+		/* [24:31] */
+		unsigned int offset_y:8;
+	} data;
+};
+
+#endif
diff --git a/drivers/media/platform/rockchip-rga/rga.c b/drivers/media/platform/rockchip-rga/rga.c
new file mode 100644
index 0000000..5ed3a48
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga.c
@@ -0,0 +1,1026 @@ 
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen <jacob-chen@iotwrt.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <linux/clk.h>
+#include <linux/debugfs.h>
+#include <linux/delay.h>
+#include <linux/fs.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/pm_runtime.h>
+#include <linux/reset.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/timer.h>
+
+#include <linux/platform_device.h>
+#include <media/v4l2-device.h>
+#include <media/v4l2-event.h>
+#include <media/v4l2-ioctl.h>
+#include <media/v4l2-mem2mem.h>
+#include <media/videobuf2-dma-sg.h>
+#include <media/videobuf2-v4l2.h>
+
+#include "rga-hw.h"
+#include "rga.h"
+
+static void job_abort(void *prv)
+{
+	struct rga_ctx *ctx = prv;
+	struct rockchip_rga *rga = ctx->rga;
+
+	if (!rga->curr)	/* No job currently running */
+		return;
+
+	wait_event_timeout(rga->irq_queue,
+			   !rga->curr, msecs_to_jiffies(RGA_TIMEOUT));
+}
+
+static void device_run(void *prv)
+{
+	struct rga_ctx *ctx = prv;
+	struct rockchip_rga *rga = ctx->rga;
+	struct vb2_buffer *src, *dst;
+	unsigned long flags;
+
+	spin_lock_irqsave(&rga->ctrl_lock, flags);
+
+	rga->curr = ctx;
+
+	src = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
+	dst = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
+
+	rga_buf_map(src);
+	rga_buf_map(dst);
+
+	rga_cmd_set(ctx);
+
+	rga_start(rga);
+
+	spin_unlock_irqrestore(&rga->ctrl_lock, flags);
+}
+
+static irqreturn_t rga_isr(int irq, void *prv)
+{
+	struct rockchip_rga *rga = prv;
+	int intr;
+
+	intr = rga_read(rga, RGA_INT) & 0xf;
+
+	rga_mod(rga, RGA_INT, intr << 4, 0xf << 4);
+
+	if (intr & 0x04) {
+		struct vb2_v4l2_buffer *src, *dst;
+		struct rga_ctx *ctx = rga->curr;
+
+		BUG_ON(!ctx);
+
+		rga->curr = NULL;
+
+		src = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
+		dst = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
+
+		BUG_ON(!src);
+		BUG_ON(!dst);
+
+		dst->timecode = src->timecode;
+		dst->vb2_buf.timestamp = src->vb2_buf.timestamp;
+		dst->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
+		dst->flags |= src->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
+
+		v4l2_m2m_buf_done(src, VB2_BUF_STATE_DONE);
+		v4l2_m2m_buf_done(dst, VB2_BUF_STATE_DONE);
+		v4l2_m2m_job_finish(rga->m2m_dev, ctx->fh.m2m_ctx);
+
+		wake_up(&rga->irq_queue);
+	}
+
+	return IRQ_HANDLED;
+}
+
+static struct v4l2_m2m_ops rga_m2m_ops = {
+	.device_run = device_run,
+	.job_abort = job_abort,
+};
+
+static int
+queue_init(void *priv, struct vb2_queue *src_vq, struct vb2_queue *dst_vq)
+{
+	struct rga_ctx *ctx = priv;
+	int ret;
+
+	src_vq->type = V4L2_BUF_TYPE_VIDEO_OUTPUT;
+	src_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+	src_vq->drv_priv = ctx;
+	src_vq->ops = &rga_qops;
+	src_vq->mem_ops = &vb2_dma_sg_memops;
+	src_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	src_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+	src_vq->lock = &ctx->rga->mutex;
+	src_vq->dev = ctx->rga->v4l2_dev.dev;
+
+	ret = vb2_queue_init(src_vq);
+	if (ret)
+		return ret;
+
+	dst_vq->type = V4L2_BUF_TYPE_VIDEO_CAPTURE;
+	dst_vq->io_modes = VB2_MMAP | VB2_DMABUF;
+	dst_vq->drv_priv = ctx;
+	dst_vq->ops = &rga_qops;
+	dst_vq->mem_ops = &vb2_dma_sg_memops;
+	dst_vq->buf_struct_size = sizeof(struct v4l2_m2m_buffer);
+	dst_vq->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_COPY;
+	dst_vq->lock = &ctx->rga->mutex;
+	dst_vq->dev = ctx->rga->v4l2_dev.dev;
+
+	return vb2_queue_init(dst_vq);
+}
+
+static int rga_s_ctrl(struct v4l2_ctrl *ctrl)
+{
+	struct rga_ctx *ctx = container_of(ctrl->handler, struct rga_ctx,
+					   ctrl_handler);
+	unsigned long flags;
+
+	spin_lock_irqsave(&ctx->rga->ctrl_lock, flags);
+	switch (ctrl->id) {
+	case V4L2_CID_PORTER_DUFF_MODE:
+		ctx->op = ctrl->val;
+		break;
+	case V4L2_CID_HFLIP:
+		ctx->hflip = ctrl->val;
+		break;
+	case V4L2_CID_VFLIP:
+		ctx->vflip = ctrl->val;
+		break;
+	case V4L2_CID_ROTATE:
+		ctx->rotate = ctrl->val;
+		break;
+	case V4L2_CID_BG_COLOR:
+		ctx->fill_color = ctrl->val;
+		break;
+	}
+	spin_unlock_irqrestore(&ctx->rga->ctrl_lock, flags);
+	return 0;
+}
+
+static const struct v4l2_ctrl_ops rga_ctrl_ops = {
+	.s_ctrl = rga_s_ctrl,
+};
+
+static int rga_setup_ctrls(struct rga_ctx *ctx)
+{
+	struct rockchip_rga *rga = ctx->rga;
+
+	v4l2_ctrl_handler_init(&ctx->ctrl_handler, 5);
+
+	v4l2_ctrl_new_std_menu(&ctx->ctrl_handler, &rga_ctrl_ops,
+			       V4L2_CID_PORTER_DUFF_MODE,
+			       V4L2_PORTER_DUFF_CLEAR, 0,
+			       V4L2_PORTER_DUFF_SRC);
+
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
+			  V4L2_CID_HFLIP, 0, 1, 1, 0);
+
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
+			  V4L2_CID_VFLIP, 0, 1, 1, 0);
+
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
+			  V4L2_CID_ROTATE, 0, 270, 90, 0);
+
+	v4l2_ctrl_new_std(&ctx->ctrl_handler, &rga_ctrl_ops,
+			  V4L2_CID_BG_COLOR, 0, 0xffffffff, 1, 0);
+
+	if (ctx->ctrl_handler.error) {
+		int err = ctx->ctrl_handler.error;
+
+		v4l2_err(&rga->v4l2_dev, "%s failed\n", __func__);
+		v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+		return err;
+	}
+
+	return 0;
+}
+
+struct rga_fmt formats[] = {
+	{
+		.fourcc = V4L2_PIX_FMT_ARGB32,
+		.color_swap = RGA_COLOR_RB_SWAP,
+		.hw_format = RGA_COLOR_FMT_ABGR8888,
+		.depth = 32,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_XRGB32,
+		.color_swap = RGA_COLOR_RB_SWAP,
+		.hw_format = RGA_COLOR_FMT_XBGR8888,
+		.depth = 32,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_ABGR32,
+		.color_swap = RGA_COLOR_ALPHA_SWAP,
+		.hw_format = RGA_COLOR_FMT_ABGR8888,
+		.depth = 32,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_XBGR32,
+		.color_swap = RGA_COLOR_ALPHA_SWAP,
+		.hw_format = RGA_COLOR_FMT_XBGR8888,
+		.depth = 32,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_RGB24,
+		.color_swap = RGA_COLOR_RB_SWAP,
+		.hw_format = RGA_COLOR_FMT_BGR888,
+		.depth = 24,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_ARGB444,
+		.color_swap = RGA_COLOR_RB_SWAP,
+		.hw_format = RGA_COLOR_FMT_ABGR4444,
+		.depth = 16,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_ARGB555,
+		.color_swap = RGA_COLOR_RB_SWAP,
+		.hw_format = RGA_COLOR_FMT_ABGR1555,
+		.depth = 16,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_RGB565,
+		.color_swap = RGA_COLOR_RB_SWAP,
+		.hw_format = RGA_COLOR_FMT_BGR565,
+		.depth = 16,
+		.uv_factor = 1,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_NV21,
+		.color_swap = RGA_COLOR_UV_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV420SP,
+		.depth = 12,
+		.uv_factor = 4,
+		.y_div = 2,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_NV61,
+		.color_swap = RGA_COLOR_UV_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV422SP,
+		.depth = 16,
+		.uv_factor = 2,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_NV12,
+		.color_swap = RGA_COLOR_NONE_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV420SP,
+		.depth = 12,
+		.uv_factor = 4,
+		.y_div = 2,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_NV16,
+		.color_swap = RGA_COLOR_NONE_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV422SP,
+		.depth = 16,
+		.uv_factor = 2,
+		.y_div = 1,
+		.x_div = 1,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_YUV420,
+		.color_swap = RGA_COLOR_NONE_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV420P,
+		.depth = 12,
+		.uv_factor = 4,
+		.y_div = 2,
+		.x_div = 2,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_YUV422P,
+		.color_swap = RGA_COLOR_NONE_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV422P,
+		.depth = 16,
+		.uv_factor = 2,
+		.y_div = 1,
+		.x_div = 2,
+	},
+	{
+		.fourcc = V4L2_PIX_FMT_YVU420,
+		.color_swap = RGA_COLOR_UV_SWAP,
+		.hw_format = RGA_COLOR_FMT_YUV420P,
+		.depth = 12,
+		.uv_factor = 4,
+		.y_div = 2,
+		.x_div = 2,
+	},
+};
+
+#define NUM_FORMATS ARRAY_SIZE(formats)
+
+struct rga_fmt *rga_fmt_find(struct v4l2_format *f)
+{
+	unsigned int i;
+
+	for (i = 0; i < NUM_FORMATS; i++) {
+		if (formats[i].fourcc == f->fmt.pix.pixelformat)
+			return &formats[i];
+	}
+	return NULL;
+}
+
+static struct rga_frame def_frame = {
+	.width = DEFAULT_WIDTH,
+	.height = DEFAULT_HEIGHT,
+	.colorspace = V4L2_COLORSPACE_DEFAULT,
+	.crop.left = 0,
+	.crop.top = 0,
+	.crop.width = DEFAULT_WIDTH,
+	.crop.height = DEFAULT_HEIGHT,
+	.fmt = &formats[0],
+};
+
+struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type)
+{
+	switch (type) {
+	case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+		return &ctx->in;
+	case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+		return &ctx->out;
+	default:
+		return ERR_PTR(-EINVAL);
+	}
+}
+
+static int rga_open(struct file *file)
+{
+	struct rockchip_rga *rga = video_drvdata(file);
+	struct rga_ctx *ctx = NULL;
+	int ret = 0;
+
+	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
+	if (!ctx)
+		return -ENOMEM;
+	ctx->rga = rga;
+	/* Set default formats */
+	ctx->in = def_frame;
+	ctx->out = def_frame;
+
+	if (mutex_lock_interruptible(&rga->mutex)) {
+		kfree(ctx);
+		return -ERESTARTSYS;
+	}
+	ctx->fh.m2m_ctx = v4l2_m2m_ctx_init(rga->m2m_dev, ctx, &queue_init);
+	if (IS_ERR(ctx->fh.m2m_ctx)) {
+		ret = PTR_ERR(ctx->fh.m2m_ctx);
+		mutex_unlock(&rga->mutex);
+		kfree(ctx);
+		return ret;
+	}
+	v4l2_fh_init(&ctx->fh, video_devdata(file));
+	file->private_data = &ctx->fh;
+	v4l2_fh_add(&ctx->fh);
+
+	rga_setup_ctrls(ctx);
+
+	/* Write the default values to the ctx struct */
+	v4l2_ctrl_handler_setup(&ctx->ctrl_handler);
+
+	ctx->fh.ctrl_handler = &ctx->ctrl_handler;
+	mutex_unlock(&rga->mutex);
+
+	return 0;
+}
+
+static int rga_release(struct file *file)
+{
+	struct rga_ctx *ctx =
+		container_of(file->private_data, struct rga_ctx, fh);
+	struct rockchip_rga *rga = ctx->rga;
+
+	mutex_lock(&rga->mutex);
+
+	v4l2_m2m_ctx_release(ctx->fh.m2m_ctx);
+
+	v4l2_ctrl_handler_free(&ctx->ctrl_handler);
+	v4l2_fh_del(&ctx->fh);
+	v4l2_fh_exit(&ctx->fh);
+	kfree(ctx);
+
+	mutex_unlock(&rga->mutex);
+
+	return 0;
+}
+
+static const struct v4l2_file_operations rga_fops = {
+	.owner = THIS_MODULE,
+	.open = rga_open,
+	.release = rga_release,
+	.poll = v4l2_m2m_fop_poll,
+	.unlocked_ioctl = video_ioctl2,
+	.mmap = v4l2_m2m_fop_mmap,
+};
+
+static int
+vidioc_querycap(struct file *file, void *priv, struct v4l2_capability *cap)
+{
+	strlcpy(cap->driver, RGA_NAME, sizeof(cap->driver));
+	strlcpy(cap->card, "rockchip-rga", sizeof(cap->card));
+	strlcpy(cap->bus_info, "platform:rga", sizeof(cap->bus_info));
+
+	return 0;
+}
+
+static int vidioc_enum_fmt(struct file *file, void *prv, struct v4l2_fmtdesc *f)
+{
+	struct rga_fmt *fmt;
+
+	if (f->index >= NUM_FORMATS)
+		return -EINVAL;
+
+	fmt = &formats[f->index];
+	f->pixelformat = fmt->fourcc;
+
+	return 0;
+}
+
+static int vidioc_g_fmt(struct file *file, void *prv, struct v4l2_format *f)
+{
+	struct rga_ctx *ctx = prv;
+	struct vb2_queue *vq;
+	struct rga_frame *frm;
+
+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+	if (!vq)
+		return -EINVAL;
+	frm = rga_get_frame(ctx, f->type);
+	if (IS_ERR(frm))
+		return PTR_ERR(frm);
+
+	f->fmt.pix.width = frm->width;
+	f->fmt.pix.height = frm->height;
+	f->fmt.pix.field = V4L2_FIELD_NONE;
+	f->fmt.pix.pixelformat = frm->fmt->fourcc;
+	f->fmt.pix.bytesperline = frm->stride;
+	f->fmt.pix.sizeimage = frm->size;
+	f->fmt.pix.colorspace = frm->colorspace;
+
+	return 0;
+}
+
+static int vidioc_try_fmt(struct file *file, void *prv, struct v4l2_format *f)
+{
+	struct rga_fmt *fmt;
+
+	fmt = rga_fmt_find(f);
+	if (!fmt) {
+		fmt = &formats[0];
+		f->fmt.pix.pixelformat = fmt->fourcc;
+	}
+
+	f->fmt.pix.field = V4L2_FIELD_NONE;
+
+	if (f->fmt.pix.width > MAX_WIDTH)
+		f->fmt.pix.width = MAX_WIDTH;
+	if (f->fmt.pix.height > MAX_HEIGHT)
+		f->fmt.pix.height = MAX_HEIGHT;
+
+	if (f->fmt.pix.width < MIN_WIDTH)
+		f->fmt.pix.width = MIN_WIDTH;
+	if (f->fmt.pix.height < MIN_HEIGHT)
+		f->fmt.pix.height = MIN_HEIGHT;
+
+	if (fmt->hw_format >= RGA_COLOR_FMT_YUV422SP)
+		f->fmt.pix.bytesperline = f->fmt.pix.width;
+	else
+		f->fmt.pix.bytesperline = (f->fmt.pix.width * fmt->depth) >> 3;
+
+	f->fmt.pix.sizeimage =
+		f->fmt.pix.height * (f->fmt.pix.width * fmt->depth) >> 3;
+
+	return 0;
+}
+
+static int vidioc_s_fmt(struct file *file, void *prv, struct v4l2_format *f)
+{
+	struct rga_ctx *ctx = prv;
+	struct rockchip_rga *rga = ctx->rga;
+	struct vb2_queue *vq;
+	struct rga_frame *frm;
+	struct rga_fmt *fmt;
+	int ret = 0;
+
+	/* Adjust all values accordingly to the hardware capabilities
+	 * and chosen format.
+	 */
+	ret = vidioc_try_fmt(file, prv, f);
+	if (ret)
+		return ret;
+	vq = v4l2_m2m_get_vq(ctx->fh.m2m_ctx, f->type);
+	if (vb2_is_busy(vq)) {
+		v4l2_err(&rga->v4l2_dev, "queue (%d) bust\n", f->type);
+		return -EBUSY;
+	}
+	frm = rga_get_frame(ctx, f->type);
+	if (IS_ERR(frm))
+		return PTR_ERR(frm);
+	fmt = rga_fmt_find(f);
+	if (!fmt)
+		return -EINVAL;
+	frm->width = f->fmt.pix.width;
+	frm->height = f->fmt.pix.height;
+	frm->size = f->fmt.pix.sizeimage;
+	frm->fmt = fmt;
+	frm->stride = f->fmt.pix.bytesperline;
+	frm->colorspace = f->fmt.pix.colorspace;
+
+	/* Reset crop settings */
+	frm->crop.left = 0;
+	frm->crop.top = 0;
+	frm->crop.width = frm->width;
+	frm->crop.height = frm->height;
+
+	return 0;
+}
+
+static int
+vidioc_try_crop(struct rga_ctx *ctx, struct v4l2_selection *s)
+{
+	struct rockchip_rga *rga = ctx->rga;
+	struct rga_frame *f;
+
+	f = rga_get_frame(ctx, s->type);
+	if (IS_ERR(f))
+		return PTR_ERR(f);
+
+	switch (s->target) {
+	case V4L2_SEL_TGT_COMPOSE:
+		/*
+		 * COMPOSE target is only valid for capture buffer type, return
+		 * error for output buffer type
+		 */
+		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+			return -EINVAL;
+		break;
+	case V4L2_SEL_TGT_CROP:
+		/*
+		 * CROP target is only valid for output buffer type, return
+		 * error for capture buffer type
+		 */
+		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+			return -EINVAL;
+		break;
+	/*
+	 * bound and default crop/compose targets are invalid targets to
+	 * try/set
+	 */
+	default:
+		return -EINVAL;
+	}
+
+	if (s->r.top < 0 || s->r.left < 0) {
+		v4l2_err(&rga->v4l2_dev,
+			 "doesn't support negative values for top & left.\n");
+		return -EINVAL;
+	}
+
+	if (s->r.left + s->r.width > s->r.width ||
+	    s->r.top + s->r.height > s->r.height ||
+	    s->r.width < MIN_WIDTH || s->r.height < MIN_HEIGHT) {
+		v4l2_err(&rga->v4l2_dev, "unsupport crop value.\n");
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+static int vidioc_g_selection(struct file *file, void *prv,
+			      struct v4l2_selection *s)
+{
+	struct rga_ctx *ctx = prv;
+	struct rga_frame *f;
+	bool use_frame = false;
+
+	f = rga_get_frame(ctx, s->type);
+	if (IS_ERR(f))
+		return PTR_ERR(f);
+
+	switch (s->target) {
+	case V4L2_SEL_TGT_COMPOSE_DEFAULT:
+	case V4L2_SEL_TGT_COMPOSE_BOUNDS:
+		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+			return -EINVAL;
+		break;
+	case V4L2_SEL_TGT_CROP_BOUNDS:
+	case V4L2_SEL_TGT_CROP_DEFAULT:
+		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+			return -EINVAL;
+		break;
+	case V4L2_SEL_TGT_COMPOSE:
+		if (s->type == V4L2_BUF_TYPE_VIDEO_OUTPUT)
+			return -EINVAL;
+		use_frame = true;
+		break;
+	case V4L2_SEL_TGT_CROP:
+		if (s->type == V4L2_BUF_TYPE_VIDEO_CAPTURE)
+			return -EINVAL;
+		use_frame = true;
+		break;
+	default:
+		return -EINVAL;
+	}
+
+	if (use_frame) {
+		s->r = f->crop;
+	} else {
+		s->r.left = 0;
+		s->r.top = 0;
+		s->r.width = f->width;
+		s->r.height = f->height;
+	}
+
+	return 0;
+}
+
+static int vidioc_s_selection(struct file *file, void *prv,
+			      struct v4l2_selection *s)
+{
+	struct rga_ctx *ctx = prv;
+	struct rga_frame *f;
+	int ret = 0;
+
+	ret = vidioc_try_crop(ctx, s);
+	if (ret)
+		return ret;
+
+	f = rga_get_frame(ctx, s->type);
+	if (IS_ERR(f))
+		return PTR_ERR(f);
+
+	f->crop = s->r;
+
+	return ret;
+}
+
+static const struct v4l2_ioctl_ops rga_ioctl_ops = {
+	.vidioc_querycap = vidioc_querycap,
+
+	.vidioc_enum_fmt_vid_cap = vidioc_enum_fmt,
+	.vidioc_g_fmt_vid_cap = vidioc_g_fmt,
+	.vidioc_try_fmt_vid_cap = vidioc_try_fmt,
+	.vidioc_s_fmt_vid_cap = vidioc_s_fmt,
+
+	.vidioc_enum_fmt_vid_out = vidioc_enum_fmt,
+	.vidioc_g_fmt_vid_out = vidioc_g_fmt,
+	.vidioc_try_fmt_vid_out = vidioc_try_fmt,
+	.vidioc_s_fmt_vid_out = vidioc_s_fmt,
+
+	.vidioc_reqbufs = v4l2_m2m_ioctl_reqbufs,
+	.vidioc_querybuf = v4l2_m2m_ioctl_querybuf,
+	.vidioc_qbuf = v4l2_m2m_ioctl_qbuf,
+	.vidioc_dqbuf = v4l2_m2m_ioctl_dqbuf,
+	.vidioc_prepare_buf = v4l2_m2m_ioctl_prepare_buf,
+	.vidioc_create_bufs = v4l2_m2m_ioctl_create_bufs,
+	.vidioc_expbuf = v4l2_m2m_ioctl_expbuf,
+
+	.vidioc_subscribe_event = v4l2_ctrl_subscribe_event,
+	.vidioc_unsubscribe_event = v4l2_event_unsubscribe,
+
+	.vidioc_streamon = v4l2_m2m_ioctl_streamon,
+	.vidioc_streamoff = v4l2_m2m_ioctl_streamoff,
+
+	.vidioc_g_selection = vidioc_g_selection,
+	.vidioc_s_selection = vidioc_s_selection,
+};
+
+static struct video_device rga_videodev = {
+	.name = "rockchip-rga",
+	.fops = &rga_fops,
+	.ioctl_ops = &rga_ioctl_ops,
+	.minor = -1,
+	.release = video_device_release,
+	.vfl_dir = VFL_DIR_M2M,
+	.device_caps = V4L2_CAP_VIDEO_M2M | V4L2_CAP_STREAMING,
+};
+
+static int rga_enable_clocks(struct rockchip_rga *rga)
+{
+	int ret;
+
+	ret = clk_prepare_enable(rga->sclk);
+	if (ret) {
+		dev_err(rga->dev, "Cannot enable rga sclk: %d\n", ret);
+		return ret;
+	}
+
+	ret = clk_prepare_enable(rga->aclk);
+	if (ret) {
+		dev_err(rga->dev, "Cannot enable rga aclk: %d\n", ret);
+		goto err_disable_sclk;
+	}
+
+	ret = clk_prepare_enable(rga->hclk);
+	if (ret) {
+		dev_err(rga->dev, "Cannot enable rga hclk: %d\n", ret);
+		goto err_disable_aclk;
+	}
+
+	return 0;
+
+err_disable_sclk:
+	clk_disable_unprepare(rga->sclk);
+err_disable_aclk:
+	clk_disable_unprepare(rga->aclk);
+
+	return ret;
+}
+
+static void rga_disable_clocks(struct rockchip_rga *rga)
+{
+	clk_disable_unprepare(rga->sclk);
+	clk_disable_unprepare(rga->hclk);
+	clk_disable_unprepare(rga->aclk);
+}
+
+static int rga_parse_dt(struct rockchip_rga *rga)
+{
+	struct reset_control *core_rst, *axi_rst, *ahb_rst;
+
+	core_rst = devm_reset_control_get(rga->dev, "core");
+	if (IS_ERR(core_rst)) {
+		dev_err(rga->dev, "failed to get core reset controller\n");
+		return PTR_ERR(core_rst);
+	}
+
+	axi_rst = devm_reset_control_get(rga->dev, "axi");
+	if (IS_ERR(axi_rst)) {
+		dev_err(rga->dev, "failed to get axi reset controller\n");
+		return PTR_ERR(axi_rst);
+	}
+
+	ahb_rst = devm_reset_control_get(rga->dev, "ahb");
+	if (IS_ERR(ahb_rst)) {
+		dev_err(rga->dev, "failed to get ahb reset controller\n");
+		return PTR_ERR(ahb_rst);
+	}
+
+	reset_control_assert(core_rst);
+	udelay(1);
+	reset_control_deassert(core_rst);
+
+	reset_control_assert(axi_rst);
+	udelay(1);
+	reset_control_deassert(axi_rst);
+
+	reset_control_assert(ahb_rst);
+	udelay(1);
+	reset_control_deassert(ahb_rst);
+
+	rga->sclk = devm_clk_get(rga->dev, "sclk");
+	if (IS_ERR(rga->sclk)) {
+		dev_err(rga->dev, "failed to get sclk clock\n");
+		return PTR_ERR(rga->sclk);
+	}
+
+	rga->aclk = devm_clk_get(rga->dev, "aclk");
+	if (IS_ERR(rga->aclk)) {
+		dev_err(rga->dev, "failed to get aclk clock\n");
+		return PTR_ERR(rga->aclk);
+	}
+
+	rga->hclk = devm_clk_get(rga->dev, "hclk");
+	if (IS_ERR(rga->hclk)) {
+		dev_err(rga->dev, "failed to get hclk clock\n");
+		return PTR_ERR(rga->hclk);
+	}
+
+	return 0;
+}
+
+static int rga_probe(struct platform_device *pdev)
+{
+	struct rockchip_rga *rga;
+	struct video_device *vfd;
+	struct resource *res;
+	int ret = 0;
+	int irq;
+
+	if (!pdev->dev.of_node)
+		return -ENODEV;
+
+	rga = devm_kzalloc(&pdev->dev, sizeof(*rga), GFP_KERNEL);
+	if (!rga)
+		return -ENOMEM;
+
+	rga->dev = &pdev->dev;
+	spin_lock_init(&rga->ctrl_lock);
+	mutex_init(&rga->mutex);
+
+	init_waitqueue_head(&rga->irq_queue);
+
+	ret = rga_parse_dt(rga);
+	if (ret)
+		dev_err(&pdev->dev, "Unable to parse OF data\n");
+
+	pm_runtime_enable(rga->dev);
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+
+	rga->regs = devm_ioremap_resource(rga->dev, res);
+	if (IS_ERR(rga->regs)) {
+		ret = PTR_ERR(rga->regs);
+		goto err_put_clk;
+	}
+
+	irq = platform_get_irq(pdev, 0);
+	if (irq < 0) {
+		dev_err(rga->dev, "failed to get irq\n");
+		ret = irq;
+		goto err_put_clk;
+	}
+
+	ret = devm_request_irq(rga->dev, irq, rga_isr, 0,
+			       dev_name(rga->dev), rga);
+	if (ret < 0) {
+		dev_err(rga->dev, "failed to request irq\n");
+		goto err_put_clk;
+	}
+
+	ret = v4l2_device_register(&pdev->dev, &rga->v4l2_dev);
+	if (ret)
+		goto err_put_clk;
+	vfd = video_device_alloc();
+	if (!vfd) {
+		v4l2_err(&rga->v4l2_dev, "Failed to allocate video device\n");
+		ret = -ENOMEM;
+		goto unreg_v4l2_dev;
+	}
+	*vfd = rga_videodev;
+	vfd->lock = &rga->mutex;
+	vfd->v4l2_dev = &rga->v4l2_dev;
+
+	video_set_drvdata(vfd, rga);
+	snprintf(vfd->name, sizeof(vfd->name), "%s", rga_videodev.name);
+	rga->vfd = vfd;
+
+	platform_set_drvdata(pdev, rga);
+	rga->m2m_dev = v4l2_m2m_init(&rga_m2m_ops);
+	if (IS_ERR(rga->m2m_dev)) {
+		v4l2_err(&rga->v4l2_dev, "Failed to init mem2mem device\n");
+		ret = PTR_ERR(rga->m2m_dev);
+		goto unreg_video_dev;
+	}
+
+	pm_runtime_get_sync(rga->dev);
+
+	rga->version.major = (rga_read(rga, RGA_VERSION_INFO) >> 24) & 0xFF;
+	rga->version.minor = (rga_read(rga, RGA_VERSION_INFO) >> 20) & 0x0F;
+
+	v4l2_info(&rga->v4l2_dev, "HW Version: 0x%02x.%02x\n",
+		  rga->version.major, rga->version.minor);
+
+	pm_runtime_put(rga->dev);
+
+	/* Create CMD buffer */
+	rga->cmdbuf_virt = dma_alloc_attrs(rga->dev, RGA_CMDBUF_SIZE,
+					   &rga->cmdbuf_phy, GFP_KERNEL,
+					   DMA_ATTR_WRITE_COMBINE);
+
+	rga->src_mmu_pages =
+		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
+	rga->dst_mmu_pages =
+		(unsigned int *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, 3);
+
+	def_frame.stride = (def_frame.width * def_frame.fmt->depth) >> 3;
+	def_frame.size = def_frame.stride * def_frame.height;
+
+	ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
+	if (ret) {
+		v4l2_err(&rga->v4l2_dev, "Failed to register video device\n");
+		goto rel_vdev;
+	}
+
+	v4l2_info(&rga->v4l2_dev, "Registered %s as /dev/%s\n",
+		  vfd->name, video_device_node_name(vfd));
+
+	return 0;
+
+rel_vdev:
+	video_device_release(vfd);
+unreg_video_dev:
+	video_unregister_device(rga->vfd);
+unreg_v4l2_dev:
+	v4l2_device_unregister(&rga->v4l2_dev);
+err_put_clk:
+	pm_runtime_disable(rga->dev);
+
+	return ret;
+}
+
+static int rga_remove(struct platform_device *pdev)
+{
+	struct rockchip_rga *rga = platform_get_drvdata(pdev);
+
+	dma_free_attrs(rga->dev, RGA_CMDBUF_SIZE, &rga->cmdbuf_virt,
+		       rga->cmdbuf_phy, DMA_ATTR_WRITE_COMBINE);
+
+	free_pages((unsigned long)rga->src_mmu_pages, 3);
+	free_pages((unsigned long)rga->dst_mmu_pages, 3);
+
+	v4l2_info(&rga->v4l2_dev, "Removing\n");
+
+	v4l2_m2m_release(rga->m2m_dev);
+	video_unregister_device(rga->vfd);
+	v4l2_device_unregister(&rga->v4l2_dev);
+
+	pm_runtime_disable(rga->dev);
+
+	return 0;
+}
+
+#ifdef CONFIG_PM
+static int rga_runtime_suspend(struct device *dev)
+{
+	struct rockchip_rga *rga = dev_get_drvdata(dev);
+
+	rga_disable_clocks(rga);
+
+	return 0;
+}
+
+static int rga_runtime_resume(struct device *dev)
+{
+	struct rockchip_rga *rga = dev_get_drvdata(dev);
+
+	return rga_enable_clocks(rga);
+}
+#endif
+
+static const struct dev_pm_ops rga_pm = {
+	SET_RUNTIME_PM_OPS(rga_runtime_suspend,
+			   rga_runtime_resume, NULL)
+};
+
+static const struct of_device_id rockchip_rga_match[] = {
+	{
+		.compatible = "rockchip,rk3288-rga",
+	},
+	{
+		.compatible = "rockchip,rk3399-rga",
+	},
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, rockchip_rga_match);
+
+static struct platform_driver rga_pdrv = {
+	.probe = rga_probe,
+	.remove = rga_remove,
+	.driver = {
+		.name = RGA_NAME,
+		.pm = &rga_pm,
+		.of_match_table = rockchip_rga_match,
+	},
+};
+
+module_platform_driver(rga_pdrv);
+
+MODULE_AUTHOR("Jacob Chen <jacob-chen@iotwrt.com>");
+MODULE_DESCRIPTION("Rockchip Raster 2d Grapphic Acceleration Unit");
+MODULE_LICENSE("GPL");
diff --git a/drivers/media/platform/rockchip-rga/rga.h b/drivers/media/platform/rockchip-rga/rga.h
new file mode 100644
index 0000000..c7d35b8
--- /dev/null
+++ b/drivers/media/platform/rockchip-rga/rga.h
@@ -0,0 +1,110 @@ 
+/*
+ * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
+ * Author: Jacob Chen <jacob-chen@iotwrt.com>
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+#ifndef __RGA_H__
+#define __RGA_H__
+
+#include <linux/platform_device.h>
+#include <media/videobuf2-v4l2.h>
+#include <media/v4l2-ctrls.h>
+#include <media/v4l2-device.h>
+
+#define RGA_NAME "rockchip-rga"
+
+struct rga_fmt {
+	u32 fourcc;
+	int depth;
+	u8 uv_factor;
+	u8 y_div;
+	u8 x_div;
+	u8 color_swap;
+	u8 hw_format;
+};
+
+struct rga_frame {
+	/* Original dimensions */
+	u32 width;
+	u32 height;
+	u32 colorspace;
+
+	/* Crop */
+	struct v4l2_rect crop;
+
+	/* Image format */
+	struct rga_fmt *fmt;
+
+	/* Variables that can calculated once and reused */
+	u32 stride;
+	u32 size;
+};
+
+struct rockchip_rga_version {
+	u32 major;
+	u32 minor;
+};
+
+struct rga_ctx {
+	struct v4l2_fh fh;
+	struct rockchip_rga *rga;
+	struct rga_frame in;
+	struct rga_frame out;
+	struct v4l2_ctrl_handler ctrl_handler;
+
+	/* Control values */
+	u32 op;
+	u32 hflip;
+	u32 vflip;
+	u32 rotate;
+	u32 fill_color;
+};
+
+struct rockchip_rga {
+	struct v4l2_device v4l2_dev;
+	struct v4l2_m2m_dev *m2m_dev;
+	struct video_device *vfd;
+
+	struct device *dev;
+	struct regmap *grf;
+	void __iomem *regs;
+	struct clk *sclk;
+	struct clk *aclk;
+	struct clk *hclk;
+	struct rockchip_rga_version version;
+
+	struct mutex mutex;
+	spinlock_t ctrl_lock;
+
+	wait_queue_head_t irq_queue;
+
+	struct rga_ctx *curr;
+	dma_addr_t cmdbuf_phy;
+	void *cmdbuf_virt;
+	unsigned int *src_mmu_pages;
+	unsigned int *dst_mmu_pages;
+};
+
+struct rga_frame *rga_get_frame(struct rga_ctx *ctx, enum v4l2_buf_type type);
+
+/* RGA Buffers Manage Part */
+extern const struct vb2_ops rga_qops;
+void rga_buf_map(struct vb2_buffer *vb);
+
+/* RGA Hardware Part */
+void rga_write(struct rockchip_rga *rga, u32 reg, u32 value);
+u32 rga_read(struct rockchip_rga *rga, u32 reg);
+void rga_mod(struct rockchip_rga *rga, u32 reg, u32 val, u32 mask);
+void rga_start(struct rockchip_rga *rga);
+
+void rga_cmd_set(struct rga_ctx *ctx);
+
+#endif