From patchwork Wed Sep 20 10:23:46 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Zabel X-Patchwork-Id: 9961261 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 119AC60234 for ; Wed, 20 Sep 2017 10:23:57 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 01BFB28F9B for ; Wed, 20 Sep 2017 10:23:57 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id EA8A628FBA; Wed, 20 Sep 2017 10:23:56 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 52FAF28F9B for ; Wed, 20 Sep 2017 10:23:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751771AbdITKXy (ORCPT ); Wed, 20 Sep 2017 06:23:54 -0400 Received: from metis.ext.4.pengutronix.de ([92.198.50.35]:51555 "EHLO metis.ext.4.pengutronix.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751747AbdITKXx (ORCPT ); Wed, 20 Sep 2017 06:23:53 -0400 Received: from lupine.hi.pengutronix.de ([2001:67c:670:100:3ad5:47ff:feaf:1a17] helo=lupine) by metis.ext.pengutronix.de with esmtp (Exim 4.84_2) (envelope-from ) id 1ducAW-0008BT-2x; Wed, 20 Sep 2017 12:23:48 +0200 Message-ID: <1505903026.7865.6.camel@pengutronix.de> Subject: Re: [PATCH 2/3] [media] tc358743: Increase FIFO level to 300. From: Philipp Zabel To: Dave Stevenson , Mauro Carvalho Chehab Cc: Mats Randgaard , Mauro Carvalho Chehab , Hans Verkuil , linux-media@vger.kernel.org Date: Wed, 20 Sep 2017 12:23:46 +0200 In-Reply-To: References: <3e638375aff788b24f988e452214649d6100a596.1505826082.git.dave.stevenson@raspberrypi.org> <1505834685.10076.5.camel@pengutronix.de> <20170919134930.6fa28562@recife.lan> X-Mailer: Evolution 3.22.6-1 Mime-Version: 1.0 X-SA-Exim-Connect-IP: 2001:67c:670:100:3ad5:47ff:feaf:1a17 X-SA-Exim-Mail-From: p.zabel@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-media@vger.kernel.org Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Hi, On Wed, 2017-09-20 at 10:14 +0100, Dave Stevenson wrote: > Hi Mauro & Philipp > > On 19 September 2017 at 17:49, Mauro Carvalho Chehab > wrote: > > Em Tue, 19 Sep 2017 17:24:45 +0200 > > Philipp Zabel escreveu: > > > > > Hi Dave, > > > > > > On Tue, 2017-09-19 at 14:08 +0100, Dave Stevenson wrote: > > > > The existing fixed value of 16 worked for UYVY 720P60 over > > > > 2 lanes at 594MHz, or UYVY 1080P60 over 4 lanes. (RGB888 > > > > 1080P60 needs 6 lanes at 594MHz). > > > > It doesn't allow for lower resolutions to work as the FIFO > > > > underflows. > > > > > > > > Using a value of 300 works for all resolutions down to VGA60, > > > > and the increase in frame delay is <4usecs for 1080P60 UYVY > > > > (2.55usecs for RGB888). > > > > > > > > Signed-off-by: Dave Stevenson > > > > > > Can we increase this to 320? This would also allow > > > 720p60 at 594 Mbps / 4 lanes, according to the xls. > > Unless I've missed something then the driver would currently request > only 2 lanes for 720p60 UYVY, and that works with the existing FIFO > setting of 16. Likewise 720p60 RGB888 requests 3 lanes and also works > on a FIFO setting of 16. > How/why were you thinking we need to run all four lanes for 720p60 > without other significant driver mods around lane config? The driver currently silently changes the number of active lanes depending on required data rate, with no way to communicate it to the receiver. The i.MX6 MIPI CSI-2 receiver driver can't cope with that, as it always activates all four lanes that are configured in the device tree. I can work around that with the following patch: ----------8<---------- Subject: [PATCH] [media] tc358743: do not dynamically reduce number of lanes Dynamic lane number reduction does not work with receivers that configure a fixed lane number according to the device tree settings. To allow 720p60 at 594 Mbit/s on 4 lanes, increase the fifo_level and tclk_trailcnt settings. Signed-off-by: Philipp Zabel --- drivers/media/i2c/tc358743.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/tc358743.c b/drivers/media/i2c/tc358743.c index 64f504542a819..70a9435928cdb 100644 --- a/drivers/media/i2c/tc358743.c +++ b/drivers/media/i2c/tc358743.c @@ -683,7 +683,7 @@ static void tc358743_set_csi(struct v4l2_subdev *sd) { struct tc358743_state *state = to_state(sd); struct tc358743_platform_data *pdata = &state->pdata; - unsigned lanes = tc358743_num_csi_lanes_needed(sd); + unsigned lanes = state->bus.num_data_lanes; v4l2_dbg(3, debug, sd, "%s:\n", __func__); @@ -1906,7 +1906,7 @@ static int tc358743_probe_of(struct tc358743_state *state) state->pdata.ddc5v_delay = DDC5V_DELAY_100_MS; state->pdata.enable_hdcp = false; /* A FIFO level of 16 should be enough for 2-lane 720p60 at 594 MHz. */ - state->pdata.fifo_level = 16; + state->pdata.fifo_level = 320; /* * The PLL input clock is obtained by dividing refclk by pll_prd. * It must be between 6 MHz and 40 MHz, lower frequency is better. @@ -1948,7 +1948,7 @@ static int tc358743_probe_of(struct tc358743_state *state) state->pdata.lptxtimecnt = 0x003; /* tclk-preparecnt: 3, tclk-zerocnt: 20 */ state->pdata.tclk_headercnt = 0x1403; - state->pdata.tclk_trailcnt = 0x00; + state->pdata.tclk_trailcnt = 0x01; /* ths-preparecnt: 3, ths-zerocnt: 1 */ state->pdata.ths_headercnt = 0x0103; state->pdata.twakeup = 0x4882;