From patchwork Fri Feb 9 06:32:36 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tim Harvey X-Patchwork-Id: 10208285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D311560245 for ; Fri, 9 Feb 2018 06:33:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C4FBC29648 for ; Fri, 9 Feb 2018 06:33:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B808B297AC; Fri, 9 Feb 2018 06:33:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4A2D629648 for ; Fri, 9 Feb 2018 06:33:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752546AbeBIGda (ORCPT ); Fri, 9 Feb 2018 01:33:30 -0500 Received: from mail-pl0-f67.google.com ([209.85.160.67]:36641 "EHLO mail-pl0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752261AbeBIGdI (ORCPT ); Fri, 9 Feb 2018 01:33:08 -0500 Received: by mail-pl0-f67.google.com with SMTP id v3so1044958plg.3 for ; Thu, 08 Feb 2018 22:33:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gateworks-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=eVvWyqkh8NHyzhkyj/h8zP27fEhT5T5yVqGz1o5TqcQ=; b=q+8tm6GUJGAIjCm6PgTC+uciz7+snJHGuXiNW2lxxNZCoIP8hhpuvchNJXOa6lisUt CfSmOL2ay7p/eGrAblTKR+mxEHfCxDMDhMctXPu7s/OD9J4pcX/v/qAVDzM3sf79p/yJ v188aXiNvvNov0RSABHNg83r8GBOOVYONUmsRfva3Mn3vlKPmxKG3vMKJapPfYg8G3E8 cYPXtMR7aONDhoIqTyCXH9yDqNpG4QGtRQRCozsp2ewujWq7fTQ/xEBQ5PqJ7cAJ7n4l kYYFnPjcrmdFE4obFM39VCYoQy6QpxDu2nfAQh+kiIYwkzOqxsMUjKwchMvcQ+SDbrbK Zd/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=eVvWyqkh8NHyzhkyj/h8zP27fEhT5T5yVqGz1o5TqcQ=; b=Ph8QK5+dKn/4eqCwM1g4EBuH7NBN2p9eL19vyYN3HS6bTbULePD3bbazULRG2eMJCn On2MqfYWYNBbbFZ8gOCS1THZz5c16SG70MRVuS8ohccsOAXFcXfCj2bsjJxkoYgZJ8WY dqQg9o6MuisS2KXiU6FqzUCksKhRt1JF4vtl2VYIsZO7s6JDuDYdfgKXL9bjm/BlgSLD 8MovmEKk1rvm/SCIl23CfW2lnixSaG6RoqnZCGZQSuwE/D8cYWhTQlajEksPNQ3vifJR ISs0KGmH5F+zlMkOeTOBN5qH+UNU2K3Fi1+iDOLMm/fh40BxkUMTy0CdtHIKlsshsS5O 4sWA== X-Gm-Message-State: APf1xPDMdI1wBm+eZm9jQRKpssidymnj9kCF1b6pIH0QmGajE/epjTQf D2gY19H7vN2OcZ/2jFCI9Xy+V3Vn X-Google-Smtp-Source: AH8x224VtDJH79ewiaqOchmOacfQy+9GA391CWUjiQbFkSynoh4/9wg/rrp9yG4uKU/yrfNDiQugoQ== X-Received: by 2002:a17:902:9003:: with SMTP id a3-v6mr1569819plp.338.1518157987646; Thu, 08 Feb 2018 22:33:07 -0800 (PST) Received: from tharvey.pdc.gateworks.com (68-189-91-139.static.snlo.ca.charter.com. [68.189.91.139]) by smtp.gmail.com with ESMTPSA id b68sm3531608pfg.159.2018.02.08.22.33.06 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Thu, 08 Feb 2018 22:33:06 -0800 (PST) From: Tim Harvey To: linux-media@vger.kernel.org, alsa-devel@alsa-project.org Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, shawnguo@kernel.org, Steve Longerbeam , Philipp Zabel , Hans Verkuil , Mauro Carvalho Chehab Subject: [PATCH v10 8/8] ARM: dts: imx: Add TDA19971 HDMI Receiver to GW551x Date: Thu, 8 Feb 2018 22:32:36 -0800 Message-Id: <1518157956-14220-9-git-send-email-tharvey@gateworks.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1518157956-14220-1-git-send-email-tharvey@gateworks.com> References: <1518157956-14220-1-git-send-email-tharvey@gateworks.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Signed-off-by: Tim Harvey --- v5: - add missing audmux config arch/arm/boot/dts/imx6qdl-gw551x.dtsi | 138 ++++++++++++++++++++++++++++++++++ 1 file changed, 138 insertions(+) diff --git a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi index 30d4662..749548a 100644 --- a/arch/arm/boot/dts/imx6qdl-gw551x.dtsi +++ b/arch/arm/boot/dts/imx6qdl-gw551x.dtsi @@ -46,6 +46,8 @@ */ #include +#include +#include / { /* these are used by bootloader for disabling nodes */ @@ -98,6 +100,50 @@ regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; }; + + sound-digital { + compatible = "simple-audio-card"; + simple-audio-card,name = "tda1997x-audio"; + + simple-audio-card,dai-link@0 { + format = "i2s"; + + cpu { + sound-dai = <&ssi2>; + }; + + codec { + bitclock-master; + frame-master; + sound-dai = <&tda1997x>; + }; + }; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; /* AUD5<->tda1997x */ + status = "okay"; + + ssi1 { + fsl,audmux-port = <0>; + fsl,port-config = < + (IMX_AUDMUX_V2_PTCR_TFSDIR | + IMX_AUDMUX_V2_PTCR_TFSEL(4+8) | /* RXFS */ + IMX_AUDMUX_V2_PTCR_TCLKDIR | + IMX_AUDMUX_V2_PTCR_TCSEL(4+8) | /* RXC */ + IMX_AUDMUX_V2_PTCR_SYN) + IMX_AUDMUX_V2_PDCR_RXDSEL(4) + >; + }; + + aud5 { + fsl,audmux-port = <4>; + fsl,port-config = < + IMX_AUDMUX_V2_PTCR_SYN + IMX_AUDMUX_V2_PDCR_RXDSEL(0)>; + }; }; &can1 { @@ -263,6 +309,60 @@ #gpio-cells = <2>; }; + tda1997x: tda1997x@48 { + compatible = "nxp,tda19971"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_tda1997x>; + reg = <0x48>; + interrupt-parent = <&gpio1>; + interrupts = <7 IRQ_TYPE_LEVEL_LOW>; + DOVDD-supply = <®_3p3>; + AVDD-supply = <®_1p8b>; + DVDD-supply = <®_1p8a>; + #sound-dai-cells = <0>; + nxp,audout-format = "i2s"; + nxp,audout-layout = <0>; + nxp,audout-width = <16>; + nxp,audout-mclk-fs = <128>; + /* + * The 8bpp YUV422 semi-planar mode outputs CbCr[11:4] + * and Y[11:4] across 16bits in the same cycle + * which we map to VP[15:08]<->CSI_DATA[19:12] + */ + nxp,vidout-portcfg = + /*G_Y_11_8<->VP[15:12]<->CSI_DATA[19:16]*/ + < TDA1997X_VP24_V15_12 TDA1997X_G_Y_11_8 >, + /*G_Y_7_4<->VP[11:08]<->CSI_DATA[15:12]*/ + < TDA1997X_VP24_V11_08 TDA1997X_G_Y_7_4 >, + /*R_CR_CBCR_11_8<->VP[07:04]<->CSI_DATA[11:08]*/ + < TDA1997X_VP24_V07_04 TDA1997X_R_CR_CBCR_11_8 >, + /*R_CR_CBCR_7_4<->VP[03:00]<->CSI_DATA[07:04]*/ + < TDA1997X_VP24_V03_00 TDA1997X_R_CR_CBCR_7_4 >; + + port { + tda1997x_to_ipu1_csi0_mux: endpoint { + remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>; + bus-width = <16>; + hsync-active = <1>; + vsync-active = <1>; + data-active = <1>; + }; + }; + }; +}; + +&ipu1_csi0_from_ipu1_csi0_mux { + bus-width = <16>; +}; + +&ipu1_csi0_mux_from_parallel_sensor { + remote-endpoint = <&tda1997x_to_ipu1_csi0_mux>; + bus-width = <16>; +}; + +&ipu1_csi0 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu1_csi0>; }; &pcie { @@ -320,6 +420,14 @@ }; &iomuxc { + pinctrl_audmux: audmuxgrp { + fsl,pins = < + MX6QDL_PAD_DISP0_DAT19__AUD5_RXD 0x130b0 + MX6QDL_PAD_DISP0_DAT14__AUD5_RXC 0x130b0 + MX6QDL_PAD_DISP0_DAT13__AUD5_RXFS 0x130b0 + >; + }; + pinctrl_flexcan1: flexcan1grp { fsl,pins = < MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b1 @@ -375,6 +483,30 @@ >; }; + pinctrl_ipu1_csi0: ipu1_csi0grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT4__IPU1_CSI0_DATA04 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__IPU1_CSI0_DATA05 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__IPU1_CSI0_DATA06 0x1b0b0 + MX6QDL_PAD_CSI0_DAT7__IPU1_CSI0_DATA07 0x1b0b0 + MX6QDL_PAD_CSI0_DAT8__IPU1_CSI0_DATA08 0x1b0b0 + MX6QDL_PAD_CSI0_DAT9__IPU1_CSI0_DATA09 0x1b0b0 + MX6QDL_PAD_CSI0_DAT10__IPU1_CSI0_DATA10 0x1b0b0 + MX6QDL_PAD_CSI0_DAT11__IPU1_CSI0_DATA11 0x1b0b0 + MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0 + MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0 + MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0 + MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0 + MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0 + MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0 + MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0 + MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0 + MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0 + MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0 + MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0 + >; + }; + pinctrl_pcie: pciegrp { fsl,pins = < MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x1b0b0 /* PCIE RST */ @@ -399,6 +531,12 @@ >; }; + pinctrl_tda1997x: tda1997xgrp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__GPIO1_IO07 0x1b0b0 + >; + }; + pinctrl_uart2: uart2grp { fsl,pins = < MX6QDL_PAD_SD4_DAT7__UART2_TX_DATA 0x1b0b1