From patchwork Fri Jun 1 20:26:04 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Vikash Garodia X-Patchwork-Id: 10444359 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 9EE946028F for ; Fri, 1 Jun 2018 20:27:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 97B2E287A7 for ; Fri, 1 Jun 2018 20:27:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8C15A28C46; Fri, 1 Jun 2018 20:27:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI, T_DKIM_INVALID autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 173EB287A7 for ; Fri, 1 Jun 2018 20:27:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753551AbeFAU0x (ORCPT ); Fri, 1 Jun 2018 16:26:53 -0400 Received: from smtp.codeaurora.org ([198.145.29.96]:53164 "EHLO smtp.codeaurora.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752572AbeFAU0r (ORCPT ); Fri, 1 Jun 2018 16:26:47 -0400 Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 79E9A6074F; Fri, 1 Jun 2018 20:26:46 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527884806; bh=uZoRNdLe7699Vi9N0hgY7Xpex5RxxZa0SfmYu6W/d1k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=iZaQ1Rf4xuAmHJbgPrhMDS9oetkSyXftawSrO3vf+0uA69D01uLJ5xqXdivhNZu20 aa7tA6xRRwQNMG8K0wH/+wz/6qplNmdU6HmkvMhfcC4GGifUEFwc31jG7x3GpmyrYe n9o7pD84TmrrhUX7kgjQYfJ1WFhzg2tg6JkduKwY= Received: from vgarodia-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: vgarodia@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 0F4E9605BD; Fri, 1 Jun 2018 20:26:41 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1527884805; bh=uZoRNdLe7699Vi9N0hgY7Xpex5RxxZa0SfmYu6W/d1k=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PRTbN3LnoPVzgwLJKBndHxhevFX7IlMHqF6YwbsLA5lsZ/QE1lPSIbidjL/lQ4jyp BMf63xV6IHXoZFyZMnyyHze1mNmqpx2L1J4zU8WJJnvYhg1ebrOefWq/0yFuAk8tT9 mcUkDfsOC3gy47/Rj7HS6+9xlThYey2/RlDULcv8= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 0F4E9605BD Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=vgarodia@codeaurora.org From: Vikash Garodia To: hverkuil@xs4all.nl, mchehab@kernel.org, robh@kernel.org, mark.rutland@arm.com, andy.gross@linaro.org, bjorn.andersson@linaro.org, stanimir.varbanov@linaro.org Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-soc@vger.kernel.org, devicetree@vger.kernel.org, vgarodia@codeaurora.org, acourbot@chromium.org Subject: [PATCH v2 1/5] media: venus: add a routine to reset ARM9 Date: Sat, 2 Jun 2018 01:56:04 +0530 Message-Id: <1527884768-22392-2-git-send-email-vgarodia@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1527884768-22392-1-git-send-email-vgarodia@codeaurora.org> References: <1527884768-22392-1-git-send-email-vgarodia@codeaurora.org> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Add a new routine to reset the ARM9 and brings it out of reset. This is in preparation to add PIL functionality in venus driver. Signed-off-by: Vikash Garodia --- drivers/media/platform/qcom/venus/firmware.c | 26 ++++++++++++++++++++++++ drivers/media/platform/qcom/venus/hfi_venus_io.h | 5 +++++ 2 files changed, 31 insertions(+) diff --git a/drivers/media/platform/qcom/venus/firmware.c b/drivers/media/platform/qcom/venus/firmware.c index 521d4b3..7d89b5a 100644 --- a/drivers/media/platform/qcom/venus/firmware.c +++ b/drivers/media/platform/qcom/venus/firmware.c @@ -14,6 +14,7 @@ #include #include +#include #include #include #include @@ -22,11 +23,36 @@ #include #include +#include "core.h" #include "firmware.h" +#include "hfi_venus_io.h" #define VENUS_PAS_ID 9 #define VENUS_FW_MEM_SIZE (6 * SZ_1M) +static void venus_reset_hw(struct venus_core *core) +{ + void __iomem *reg_base = core->base; + + writel(0, reg_base + WRAPPER_FW_START_ADDR); + writel(VENUS_FW_MEM_SIZE, reg_base + WRAPPER_FW_END_ADDR); + writel(0, reg_base + WRAPPER_CPA_START_ADDR); + writel(VENUS_FW_MEM_SIZE, reg_base + WRAPPER_CPA_END_ADDR); + writel(0x0, reg_base + WRAPPER_CPU_CGC_DIS); + writel(0x0, reg_base + WRAPPER_CPU_CLOCK_CONFIG); + + /* Make sure all register writes are committed. */ + mb(); + + /* + * Need to wait 10 cycles of internal clocks before bringing ARM9 + * out of reset. + */ + udelay(1); + + /* Bring Arm9 out of reset */ + writel_relaxed(0, reg_base + WRAPPER_A9SS_SW_RESET); +} int venus_boot(struct device *dev, const char *fwname) { const struct firmware *mdt; diff --git a/drivers/media/platform/qcom/venus/hfi_venus_io.h b/drivers/media/platform/qcom/venus/hfi_venus_io.h index 76f4793..39afa5d 100644 --- a/drivers/media/platform/qcom/venus/hfi_venus_io.h +++ b/drivers/media/platform/qcom/venus/hfi_venus_io.h @@ -109,6 +109,11 @@ #define WRAPPER_CPU_CGC_DIS (WRAPPER_BASE + 0x2010) #define WRAPPER_CPU_STATUS (WRAPPER_BASE + 0x2014) #define WRAPPER_SW_RESET (WRAPPER_BASE + 0x3000) +#define WRAPPER_CPA_START_ADDR (WRAPPER_BASE + 0x1020) +#define WRAPPER_CPA_END_ADDR (WRAPPER_BASE + 0x1024) +#define WRAPPER_FW_START_ADDR (WRAPPER_BASE + 0x1028) +#define WRAPPER_FW_END_ADDR (WRAPPER_BASE + 0x102C) +#define WRAPPER_A9SS_SW_RESET (WRAPPER_BASE + 0x3000) /* Venus 4xx */ #define WRAPPER_VCODEC0_MMCC_POWER_STATUS (WRAPPER_BASE + 0x90)