From patchwork Thu Jan 17 05:39:18 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 10767533 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 38B9917FB for ; Thu, 17 Jan 2019 05:39:58 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 284E92EC19 for ; Thu, 17 Jan 2019 05:39:58 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 1C9B42EC34; Thu, 17 Jan 2019 05:39:58 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C14A42EC19 for ; Thu, 17 Jan 2019 05:39:57 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729374AbfAQFjg (ORCPT ); Thu, 17 Jan 2019 00:39:36 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:19686 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1729370AbfAQFjg (ORCPT ); Thu, 17 Jan 2019 00:39:36 -0500 X-UUID: a5dbe9b327d945b591f9167c78c9d838-20190117 X-UUID: a5dbe9b327d945b591f9167c78c9d838-20190117 Received: from mtkcas08.mediatek.inc [(172.21.101.126)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1958811014; Thu, 17 Jan 2019 13:39:27 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 17 Jan 2019 13:39:25 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 17 Jan 2019 13:39:25 +0800 From: Yunfei Dong To: Tiffany Lin , Andrew-CT Chen , Rob Herring CC: Yunfei Dong , Mauro Carvalho Chehab , Mark Rutland , Matthias Brugger , , , , , , Qianqian Yan Subject: [PATCH v3,1/3] media: dt-bindings: media: add 'assigned-clocks' to vcodec examples Date: Thu, 17 Jan 2019 13:39:18 +0800 Message-ID: <1547703560-16195-1-git-send-email-yunfei.dong@mediatek.com> X-Mailer: git-send-email 1.7.9.5 MIME-Version: 1.0 X-TM-SNTS-SMTP: 3CD434C3B5ED7A540F4A79D3232CFAE402E6880ACB5F90B220D8CFD89672F5302000:8 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Fix MTK binding document for MT8173 dtsi changed in order to use standard CCF interface. MT8173 SoC from Mediatek. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan Reviewed-by: Rob Herring --- .../devicetree/bindings/media/mediatek-vcodec.txt | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt index 2a615d84a682..b6b5dde6abd8 100644 --- a/Documentation/devicetree/bindings/media/mediatek-vcodec.txt +++ b/Documentation/devicetree/bindings/media/mediatek-vcodec.txt @@ -66,6 +66,15 @@ vcodec_dec: vcodec@16000000 { "vencpll", "venc_lt_sel", "vdec_bus_clk_src"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_VCODECPLL>; + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; }; vcodec_enc: vcodec@18002000 { @@ -105,4 +114,8 @@ vcodec_dec: vcodec@16000000 { "venc_sel", "venc_lt_sel_src", "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, + <&topckgen CLK_TOP_UNIVPLL1_D2>; };