From patchwork Thu Feb 14 02:24:52 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yunfei Dong X-Patchwork-Id: 10811617 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id C6ED013BF for ; Thu, 14 Feb 2019 02:25:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A559D2E1CE for ; Thu, 14 Feb 2019 02:25:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 95B852E1D9; Thu, 14 Feb 2019 02:25:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 47B9D2E1CE for ; Thu, 14 Feb 2019 02:25:09 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S2392024AbfBNCZD (ORCPT ); Wed, 13 Feb 2019 21:25:03 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:32871 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1733149AbfBNCZD (ORCPT ); Wed, 13 Feb 2019 21:25:03 -0500 X-UUID: df58f4af15454ef18c3e1a06c020d510-20190214 X-UUID: df58f4af15454ef18c3e1a06c020d510-20190214 Received: from mtkcas09.mediatek.inc [(172.21.101.178)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 1806646010; Thu, 14 Feb 2019 10:24:58 +0800 Received: from MTKCAS06.mediatek.inc (172.21.101.30) by mtkmbs08n2.mediatek.inc (172.21.101.56) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 14 Feb 2019 10:24:56 +0800 Received: from localhost.localdomain (10.17.3.153) by MTKCAS06.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 14 Feb 2019 10:24:55 +0800 From: Yunfei Dong To: Hans Verkuil , Tiffany Lin , Andrew-CT Chen , Rob Herring CC: Yunfei Dong , Mauro Carvalho Chehab , Mark Rutland , Matthias Brugger , , , , , , Qianqian Yan Subject: [RESEND PATCH v4,2/3] arm64: dts: Using standard CCF interface to set vcodec clk Date: Thu, 14 Feb 2019 10:24:52 +0800 Message-ID: <1550111093-7057-2-git-send-email-yunfei.dong@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1550111093-7057-1-git-send-email-yunfei.dong@mediatek.com> References: <1550111093-7057-1-git-send-email-yunfei.dong@mediatek.com> MIME-Version: 1.0 X-TM-SNTS-SMTP: 505ED9FBFA238E16F710D7103E13967DF4CCD8A4E801243108565D5607A8E1F02000:8 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Using standard CCF interface to set vdec/venc parent clk and clk rate. Signed-off-by: Yunfei Dong Signed-off-by: Qianqian Yan --- arch/arm64/boot/dts/mediatek/mt8173.dtsi | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi index 412ffd4..126d11e 100644 --- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi @@ -1305,6 +1305,15 @@ "vencpll", "venc_lt_sel", "vdec_bus_clk_src"; + assigned-clocks = <&topckgen CLK_TOP_VENC_LT_SEL>, + <&topckgen CLK_TOP_CCI400_SEL>, + <&topckgen CLK_TOP_VDEC_SEL>, + <&apmixedsys CLK_APMIXED_VCODECPLL>, + <&apmixedsys CLK_APMIXED_VENCPLL>; + assigned-clock-parents = <&topckgen CLK_TOP_VCODECPLL_370P5>, + <&topckgen CLK_TOP_UNIVPLL_D2>, + <&topckgen CLK_TOP_VCODECPLL>; + assigned-clock-rates = <0>, <0>, <0>, <1482000000>, <800000000>; }; larb1: larb@16010000 { @@ -1370,6 +1379,10 @@ "venc_sel", "venc_lt_sel_src", "venc_lt_sel"; + assigned-clocks = <&topckgen CLK_TOP_VENC_SEL>, + <&topckgen CLK_TOP_VENC_LT_SEL>; + assigned-clock-parents = <&topckgen CLK_TOP_VENCPLL_D2>, + <&topckgen CLK_TOP_UNIVPLL1_D2>; }; vencltsys: clock-controller@19000000 {