From patchwork Thu Jun 6 10:00:32 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Louis Kuo X-Patchwork-Id: 10979119 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 78CC66C5 for ; Thu, 6 Jun 2019 10:01:00 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 68AB62886B for ; Thu, 6 Jun 2019 10:01:00 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5CAAD28862; Thu, 6 Jun 2019 10:01:00 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 00E1E1FFE4 for ; Thu, 6 Jun 2019 10:00:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728009AbfFFKA7 (ORCPT ); Thu, 6 Jun 2019 06:00:59 -0400 Received: from mailgw02.mediatek.com ([210.61.82.184]:27293 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727948AbfFFKA6 (ORCPT ); Thu, 6 Jun 2019 06:00:58 -0400 X-UUID: 1d262d57566941e9b07f5460b33bf28a-20190606 X-UUID: 1d262d57566941e9b07f5460b33bf28a-20190606 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw02.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 68917604; Thu, 06 Jun 2019 18:00:43 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Thu, 6 Jun 2019 18:00:41 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Thu, 6 Jun 2019 18:00:41 +0800 From: Louis Kuo To: , , , , , CC: , , , , , , , , , , , , , , , Louis Kuo Subject: [RFC PATCH V3 3/4] dt-bindings: mt8183: Add sensor interface dt-bindings Date: Thu, 6 Jun 2019 18:00:32 +0800 Message-ID: <1559815233-24796-4-git-send-email-louis.kuo@mediatek.com> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1559815233-24796-1-git-send-email-louis.kuo@mediatek.com> References: <1559815233-24796-1-git-send-email-louis.kuo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the DT binding documentation for the sensor interface module in Mediatek SoCs. Signed-off-by: Louis Kuo --- .../devicetree/bindings/media/mediatek-seninf.txt | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-seninf.txt b/Documentation/devicetree/bindings/media/mediatek-seninf.txt new file mode 100644 index 0000000..979063a --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-seninf.txt @@ -0,0 +1,31 @@ +* Mediatek seninf MIPI-CSI2 host driver + +Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support a widely adopted, +simple, high-speed protocol primarily intended for point-to-point image and video +transmission between cameras and host devices. + +Required properties: + - compatible: "mediatek,mt8183-seninf" + - reg: Must contain an entry for each entry in reg-names. + - reg-names: Must include the following entries: + "base_reg": seninf registers base + "rx_reg": Rx analog registers base + - interrupts: interrupt number to the cpu. + - clocks : clock name from clock manager + - clock-names: must be CLK_CAM_SENINF and CLK_TOP_MUX_SENINF. + It is the clocks of seninf + +Example: + seninf: seninf@1a040000 { + compatible = "mediatek,mt8183-seninf"; + reg = <0 0x1a040000 0 0x8000>, + <0 0x11C80000 0 0x6000>; + reg-names = "base_reg", "rx_reg"; + interrupts = ; + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; + clocks = + <&camsys CLK_CAM_SENINF>, <&topckgen CLK_TOP_MUX_SENINF>; + clock-names = + "CLK_CAM_SENINF", "CLK_TOP_MUX_SENINF"; + } +