From patchwork Fri Jul 31 09:02:40 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sowjanya Komatineni X-Patchwork-Id: 11694491 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 30486913 for ; Fri, 31 Jul 2020 09:03:25 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 16A9322CA1 for ; Fri, 31 Jul 2020 09:03:25 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=nvidia.com header.i=@nvidia.com header.b="r37jliP3" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1732063AbgGaJC7 (ORCPT ); Fri, 31 Jul 2020 05:02:59 -0400 Received: from hqnvemgate26.nvidia.com ([216.228.121.65]:16312 "EHLO hqnvemgate26.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731989AbgGaJC4 (ORCPT ); Fri, 31 Jul 2020 05:02:56 -0400 Received: from hqpgpgate101.nvidia.com (Not Verified[216.228.121.13]) by hqnvemgate26.nvidia.com (using TLS: TLSv1.2, DES-CBC3-SHA) id ; Fri, 31 Jul 2020 02:02:42 -0700 Received: from hqmail.nvidia.com ([172.20.161.6]) by hqpgpgate101.nvidia.com (PGP Universal service); Fri, 31 Jul 2020 02:02:55 -0700 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Fri, 31 Jul 2020 02:02:55 -0700 Received: from HQMAIL111.nvidia.com (172.20.187.18) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3; Fri, 31 Jul 2020 09:02:55 +0000 Received: from hqnvemgw03.nvidia.com (10.124.88.68) by HQMAIL111.nvidia.com (172.20.187.18) with Microsoft SMTP Server (TLS) id 15.0.1473.3 via Frontend Transport; Fri, 31 Jul 2020 09:02:55 +0000 Received: from skomatineni-linux.nvidia.com (Not Verified[10.2.167.221]) by hqnvemgw03.nvidia.com with Trustwave SEG (v7,5,8,10121) id ; Fri, 31 Jul 2020 02:02:54 -0700 From: Sowjanya Komatineni To: , , , , , , , CC: , , , , , , , Subject: [RFC PATCH v6 01/10] media: tegra-video: Fix channel format alignment Date: Fri, 31 Jul 2020 02:02:40 -0700 Message-ID: <1596186169-18729-2-git-send-email-skomatineni@nvidia.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1596186169-18729-1-git-send-email-skomatineni@nvidia.com> References: <1596186169-18729-1-git-send-email-skomatineni@nvidia.com> X-NVConfidentiality: public MIME-Version: 1.0 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nvidia.com; s=n1; t=1596186162; bh=8GJbUvoTqNXQhoilqMQO06MgCPv5IgO6eahUeR7/0ig=; h=X-PGP-Universal:From:To:CC:Subject:Date:Message-ID:X-Mailer: In-Reply-To:References:X-NVConfidentiality:MIME-Version: Content-Type; b=r37jliP3vXsz1elhbfJE7cg7Lj36Q6LYjLTWYHa4T/bXGfVrZUyNRVuBrCCAwBy+H bkgyUY1w1ene7McgEmTlgsc5pew7hyecVgTXQ0MaBdx0Yc/PRs/GiqpN2RS5pMaKfF RFGxa+WtaoBCDcQb8arOrR9QZvhcnFO3jxxDUlWlX62z6kkDHyfJbewV/g1Q7JW//7 7ho+H+gPjQAmwi4Oy6L7fhO8lifsVZAHGE/wu5OyPGYROa9cjGAhULwhUibyUeoWRS NacWrddys0lnt4k7zwh5eut0kuqwz/lesORaYC8LkmOyqFT8jny+GByc87ZIiyjHlg P3cIlo/xXrdPA== Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Pixel format width is mistakenly aligned to surface align bytes and altering width to aligned value may force sensor mode change other than the requested one and also cause mismatch in width programmed between sensor and vi which can lead to capture errors. This patch removes width alignment and clamps width as per Tegra minimum and maximum limits. Signed-off-by: Sowjanya Komatineni --- drivers/staging/media/tegra-video/vi.c | 16 +++------------- 1 file changed, 3 insertions(+), 13 deletions(-) diff --git a/drivers/staging/media/tegra-video/vi.c b/drivers/staging/media/tegra-video/vi.c index 1b5e660..d621ebc 100644 --- a/drivers/staging/media/tegra-video/vi.c +++ b/drivers/staging/media/tegra-video/vi.c @@ -359,25 +359,15 @@ static void tegra_channel_fmt_align(struct tegra_vi_channel *chan, struct v4l2_pix_format *pix, unsigned int bpp) { - unsigned int align; - unsigned int min_width; - unsigned int max_width; - unsigned int width; unsigned int min_bpl; unsigned int max_bpl; unsigned int bpl; /* - * The transfer alignment requirements are expressed in bytes. Compute - * minimum and maximum values, clamp the requested width and convert - * it back to pixels. Use bytesperline to adjust the width. + * The transfer alignment requirements are expressed in bytes. + * Clamp the requested width and height to the limits. */ - align = lcm(SURFACE_ALIGN_BYTES, bpp); - min_width = roundup(TEGRA_MIN_WIDTH, align); - max_width = rounddown(TEGRA_MAX_WIDTH, align); - width = roundup(pix->width * bpp, align); - - pix->width = clamp(width, min_width, max_width) / bpp; + pix->width = clamp(pix->width, TEGRA_MIN_WIDTH, TEGRA_MAX_WIDTH); pix->height = clamp(pix->height, TEGRA_MIN_HEIGHT, TEGRA_MAX_HEIGHT); /* Clamp the requested bytes per line value. If the maximum bytes per