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Wed, 17 Mar 2021 03:57:26 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org Cc: airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, mchehab@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, kishon@ti.com, vkoul@kernel.org, robert.foss@linaro.org, lee.jones@linaro.org Subject: [PATCH v6 11/14] dt-bindings: display: bridge: Add i.MX8qm/qxp LVDS display bridge binding Date: Wed, 17 Mar 2021 11:42:46 +0800 Message-Id: <1615952569-4711-12-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1615952569-4711-1-git-send-email-victor.liu@nxp.com> References: <1615952569-4711-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: HK2PR04CA0090.apcprd04.prod.outlook.com (2603:1096:202:15::34) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by HK2PR04CA0090.apcprd04.prod.outlook.com (2603:1096:202:15::34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3955.18 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Eb8OVGUNyxsFk0gkfBJIy2mjZWdLBugtYTrw9+eis8p5D20BPBhiOpsh5g1++ryx6qZytWs/d6vkTQX1sYslRrKPYhHpes0QqQoB3vt16FtIGwuq8z49nvroR68di0VCc6U9IQvXu38iDzDtQUsDgxX/uAyvwO/jXG2H3snO90p3xgiBfJs38cd0wlVdSY8sldZRiDIS+fFc02QBOyy9fj0BOs4n93mOszLVBOJzBVhxBd6CFZhiKGDy8Ii37zVO4Gikp9lmwillYb9uFomxQpa5dphRQdGEl0/2++xk4cSkkbamUE4s5ISqFxTGV0PvLtEWkgLWEeVzDtIRCMfRQbXi46Ix1NbOoMZS02UeJywfNCtgAarhVsEQgwjXkPEEu9W8udc/9N0UeUf70GOMw/uYU7FS7Hw5gDTXRMu1MstLtXEcDaegpGBgFgqkZamfHD1aSFr4XJuzkcdFwoa+yjdqyGrsfKd6l4xq+6voJPixqACq5tZBARUZrKj8RDRaLvppFlmDxuWH5YbCfJiYJ//CRwgjBOJ84k0knhCMWLpDDLSJxpPlHUBR38j9/6hkaezXXfeprfuDuLFbgIlVca3sMBnZOyecy14LyGEEmp1mdxdHCUA/mbSQU3xqKU2HyEqGC0rb5wyDbboO30UgxGslDTd5TGY5Wae7xGKzwYsY0aX5CAfoGQ7MzbmQrlsuDKABR1Bms4mwokfa6JTZnrzMlyhIXmAEJZsJ9ezBWuPKdrvqZPhedxxznSMF0fN2uTmMQa2MNDgGs/YjwXIlgSmFEZwJ92zMJr1PPEcd4DpugPBdbcZgh4HCrMH7sGNQLjilbX168jD1M2WdJxD7GhPTv/oFza8hXaah1xH/kxIfE2LxTwbFbu3gRjnVjMOjEDJxQRRlMhcHZ/RF3Dd7zoc80fvErKwvG2PSeLa7P4+71S0drQrLiZOANbN0G8EIBjJDcdDx97uLBCvDG8A2diIZPdSH3//Til0OeeqKD0GcR5/5vlOLMtqJkBVBRA8KsIGG4EShl+U9bum947R6QH9Y5Jq0OdfhO833RMc5ZQdD5BIajeIBPpBDK9b+RU4KkaemvyQ6NVCwOHnYsWEBNuQ/bOGyX/hnt4bAJClBALkdN6Kh3U1mjhqCpHKyoVQPxAbwvQSY6VfJjsrSfwcXZRQRbbtgyotCiEYDVi9t4Kltd67c+Dk3gi6GEDk2KVp+fvEythBeg4b2/GSbecBAJt6d1UIlJI96RGMUNxySn6XL1tsM/djNZJlDBgvDiUA1qv2WSHF+YbeysvEKWyqjOoGH6SvpQQoXsv1dTiQCitVkUNQFphziGWrdruDSAkcZ X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 56bab68b-cc85-4e45-b6a2-08d8e8f8c712 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 17 Mar 2021 03:57:26.4249 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: ZtsobAQLvEJk/fD7CmjlaprQNYV6AKVgT8FsPzbKimDXsthif83SJczJcQVX7FnzHfw3AFzlMJO5ztEjrlufZw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VI1PR04MB6141 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds bindings for i.MX8qm/qxp LVDS display bridge(LDB). Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v5->v6: * No change. v4->v5: * No change. v3->v4: * Add Rob's R-b tag. v2->v3: * Drop 'fsl,syscon' property. (Rob) * Mention the CSR module controls LDB. v1->v2: * Use graph schema. (Laurent) * Side note i.MX8qxp LDB official name 'pixel mapper'. (Laurent) .../bindings/display/bridge/fsl,imx8qxp-ldb.yaml | 173 +++++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml new file mode 100644 index 00000000..9454300 --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-ldb.yaml @@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-ldb.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp LVDS Display Bridge + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp LVDS Display Bridge(LDB) has two channels. + + The i.MX8qm/qxp LDB is controlled by Control and Status Registers(CSR) module. + The CSR module, as a system controller, contains the LDB's configuration + registers. + + For i.MX8qxp LDB, each channel supports up to 24bpp parallel input color + format and can map the input to VESA or JEIDA standards. The two channels + cannot be used simultaneously, that is to say, the user should pick one of + them to use. Two LDB channels from two LDB instances can work together in + LDB split mode to support a dual link LVDS display. The channel indexes + have to be different. Channel0 outputs odd pixels and channel1 outputs + even pixels. + + For i.MX8qm LDB, each channel additionally supports up to 30bpp parallel + input color format. The two channels can be used simultaneously, either + in dual mode or split mode. In dual mode, the two channels output identical + data. In split mode, channel0 outputs odd pixels and channel1 outputs even + pixels. + + A side note is that i.MX8qm/qxp LDB is officially called pixel mapper in + the SoC reference manuals. The pixel mapper uses logic of LDBs embedded in + i.MX6qdl/sx SoCs, i.e., it is essentially based on them. To keep the naming + consistency, this binding calls it LDB. + +properties: + compatible: + enum: + - fsl,imx8qm-ldb + - fsl,imx8qxp-ldb + + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + clocks: + items: + - description: pixel clock + - description: bypass clock + + clock-names: + items: + - const: pixel + - const: bypass + + power-domains: + maxItems: 1 + + fsl,companion-ldb: + $ref: /schemas/types.yaml#/definitions/phandle + description: | + A phandle which points to companion LDB which is used in LDB split mode. + +patternProperties: + "^channel@[0-1]$": + type: object + description: Represents a channel of LDB. + + properties: + "#address-cells": + const: 1 + + "#size-cells": + const: 0 + + reg: + description: The channel index. + enum: [ 0, 1 ] + + phys: + description: A phandle to the phy module representing the LVDS PHY. + maxItems: 1 + + phy-names: + const: lvds_phy + + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: Input port of the channel. + + port@1: + $ref: /schemas/graph.yaml#/properties/port + description: Output port of the channel. + + required: + - "#address-cells" + - "#size-cells" + - reg + - phys + - phy-names + + additionalProperties: false + +required: + - compatible + - "#address-cells" + - "#size-cells" + - clocks + - clock-names + - power-domains + - channel@0 + - channel@1 + +allOf: + - if: + properties: + compatible: + contains: + const: fsl,imx8qm-ldb + then: + properties: + fsl,companion-ldb: false + +additionalProperties: false + +examples: + - | + #include + ldb { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx8qxp-ldb"; + clocks = <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_MISC2>, + <&clk IMX_SC_R_LVDS_0 IMX_SC_PM_CLK_BYPASS>; + clock-names = "pixel", "bypass"; + power-domains = <&pd IMX_SC_R_LVDS_0>; + + channel@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch0_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch0>; + }; + }; + }; + + channel@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + phys = <&mipi_lvds_0_phy>; + phy-names = "lvds_phy"; + + port@0 { + reg = <0>; + + mipi_lvds_0_ldb_ch1_mipi_lvds_0_pxl2dpi: endpoint { + remote-endpoint = <&mipi_lvds_0_pxl2dpi_mipi_lvds_0_ldb_ch1>; + }; + }; + }; + };