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Wed, 31 Mar 2021 06:49:01 +0000 From: Liu Ying To: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-media@vger.kernel.org Cc: airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, mchehab@kernel.org, a.hajda@samsung.com, narmstrong@baylibre.com, Laurent.pinchart@ideasonboard.com, jonas@kwiboo.se, jernej.skrabec@siol.net, kishon@ti.com, vkoul@kernel.org, robert.foss@linaro.org, lee.jones@linaro.org, marcel.ziswiler@toradex.com Subject: [PATCH v7 05/14] dt-bindings: display: bridge: Add i.MX8qm/qxp display pixel link binding Date: Wed, 31 Mar 2021 14:33:16 +0800 Message-Id: <1617172405-12962-6-git-send-email-victor.liu@nxp.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1617172405-12962-1-git-send-email-victor.liu@nxp.com> References: <1617172405-12962-1-git-send-email-victor.liu@nxp.com> X-Originating-IP: [119.31.174.66] X-ClientProxiedBy: MA1PR01CA0105.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::21) To VI1PR04MB3983.eurprd04.prod.outlook.com (2603:10a6:803:4c::16) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from localhost.localdomain (119.31.174.66) by MA1PR01CA0105.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a00:1::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.20.3977.26 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData: Rdb+ce4OSgMGbVd9kqGaKQbo/5Du3eucZE6hcS+pFZ5Ygx4YWc1De7PJ0h9teNPNtG2H2YXoxq/bN+A05LXIyxdR1b4WOXHGt1n1Hzqj97J6UMbsMxVJoRrxkN5qSK17Igjdkeh60G+6bhFZO+fsdjfnGU6EQ2nUiYCiwO6Th4fiKPPG/KQv8BIOq1dXcelSW3X+g5S06ncwr22iIqmrADLnaWhLrHyEyqqaBlqog9ULqRGuUxwc9sTrO+n0gadbZwM6PwgjUJw645Xoexs307t4rQXAhG2g8/Qb1DtmOJlnlEmnWmsFvgCyj00ibNeBYZOve63D7eCEQby/HJb05jAtk/pnWsZ2gXChMV04FRR4z/uUWJH7KXIMFnZFgKm0I48nmtyu+scJOxAB1SJTM0fkk+2YVmJqQD+wWK2zOdJ49azLZMDdLb1k3Qd3jGA6Qxrs4QbhQofppEvbGMnVcxB9gCYaN1jXSqRWRCh9+V11DkLfGvVumtCGaZvFFLTqnjER0MjPnwVFhycDaRT1FJgNjYViw0XaSjzE1bLmZR3dUEz0Vr5ldW9PA66+vKe6m+bCuB2lHeayp1cdHf4yo7zhauaMUSG53pRfpKQm7INu3KwqTilc5JCqbhrVS2oTVArG8zFtVK0f+zuGUz90H6H2LUttHmhCj69KE2i7cFmhs4cKC2UMhHa1+Df6IYdDOs/h+smtU9AKyE6/02sFcMfCa6LvMi4fdUeTxG5xlTn+1xJ1DSa5Li1/kx+6UItjJfI3ipS8Rsj1KwV0pxj20ov/xJOL7qzFvrwNt+Vm6a6v8Ybk7C1AbL6CyhCSHKwfEBMt1ZxCbQ3wOFDrO/Suwni2ReKgIx+P+5Qkdh9Yky1Zow38RDY2rC6gDzdhlXnxbrU7D9pO3lK7DBVouGvMo0EE+fVWrlAkaZ7YCblTDL2fUK38Pt8sORB+EzNvWnwcyXLf82XKABfG1dgLdGvKxQ+cH3kSvqOSJASdo5nqTi9V8EcXpKAF4ALcabFQRpM2WfhvwGiQEugd/90P3qdJp8b74ll5AOCDwevFHSvVb3ggzI93IU5GIAIJ+j/u1F5GMOmEcc+P5BYHBtpknMHiFNtEA7IfmwwEpBYDCGh6pfACN9NtEdNGsmJn/2+tcjVpL1yXZAYEOuXTByrzODDmngiCpc7KB2NyaVUY7kqQ0azklZM/LHL6RG8bYoHGWhvrobfkqtEvXa5OAyMVfY0p2EnPG8tzNQ0QTc+TKDBGVEWN9O+4Kh4ACJa6CwCsU/hUef7OYLaWL62+MwPtWJ7LZfL9jclvm73ycNOKScU9N+vSKYGWjT89YCY7T8S2IGw8 X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: ee6b21e0-a9d8-458f-eb1b-08d8f41110e1 X-MS-Exchange-CrossTenant-AuthSource: VI1PR04MB3983.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 31 Mar 2021 06:49:01.1045 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: e1a7y0dSL9PwHBUUq1CfC64GbQO5zNMRYt3ycqj++YngGQbM+GsKkC6BB7ZL/wV7OYo+QBvEYjcjMiUKW6LmmQ== X-MS-Exchange-Transport-CrossTenantHeadersStamped: VE1PR04MB6349 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org This patch adds bindings for i.MX8qm/qxp display pixel link. Reviewed-by: Rob Herring Signed-off-by: Liu Ying --- v6->v7: * No change. v5->v6: * No change. v4->v5: * No change. v3->v4: * No change. v2->v3: * Add Rob's R-b tag. v1->v2: * Use graph schema. (Laurent) * Require all four pixel link output ports. (Laurent) * Mention pixel link is accessed via SCU firmware. (Rob) .../display/bridge/fsl,imx8qxp-pixel-link.yaml | 106 +++++++++++++++++++++ 1 file changed, 106 insertions(+) create mode 100644 Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml diff --git a/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml new file mode 100644 index 00000000..3af67cc --- /dev/null +++ b/Documentation/devicetree/bindings/display/bridge/fsl,imx8qxp-pixel-link.yaml @@ -0,0 +1,106 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/bridge/fsl,imx8qxp-pixel-link.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale i.MX8qm/qxp Display Pixel Link + +maintainers: + - Liu Ying + +description: | + The Freescale i.MX8qm/qxp Display Pixel Link(DPL) forms a standard + asynchronous linkage between pixel sources(display controller or + camera module) and pixel consumers(imaging or displays). + It consists of two distinct functions, a pixel transfer function and a + control interface. Multiple pixel channels can exist per one control channel. + This binding documentation is only for pixel links whose pixel sources are + display controllers. + + The i.MX8qm/qxp Display Pixel Link is accessed via System Controller Unit(SCU) + firmware. + +properties: + compatible: + enum: + - fsl,imx8qm-dc-pixel-link + - fsl,imx8qxp-dc-pixel-link + + ports: + $ref: /schemas/graph.yaml#/properties/ports + + properties: + port@0: + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link input port node from upstream video source. + + patternProperties: + "^port@[1-4]$": + $ref: /schemas/graph.yaml#/properties/port + description: The pixel link output port node to downstream bridge. + + required: + - port@0 + - port@1 + - port@2 + - port@3 + - port@4 + +required: + - compatible + - ports + +additionalProperties: false + +examples: + - | + dc0-pixel-link0 { + compatible = "fsl,imx8qxp-dc-pixel-link"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* from dc0 pixel combiner channel0 */ + port@0 { + reg = <0>; + + dc0_pixel_link0_dc0_pixel_combiner_ch0: endpoint { + remote-endpoint = <&dc0_pixel_combiner_ch0_dc0_pixel_link0>; + }; + }; + + /* to PXL2DPIs in MIPI/LVDS combo subsystems */ + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + dc0_pixel_link0_mipi_lvds_0_pxl2dpi: endpoint@0 { + reg = <0>; + remote-endpoint = <&mipi_lvds_0_pxl2dpi_dc0_pixel_link0>; + }; + + dc0_pixel_link0_mipi_lvds_1_pxl2dpi: endpoint@1 { + reg = <1>; + remote-endpoint = <&mipi_lvds_1_pxl2dpi_dc0_pixel_link0>; + }; + }; + + /* unused */ + port@2 { + reg = <2>; + }; + + /* unused */ + port@3 { + reg = <3>; + }; + + /* to imaging subsystem */ + port@4 { + reg = <4>; + }; + }; + };