From patchwork Mon Dec 13 13:04:09 2010 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jean-Francois Moine X-Patchwork-Id: 406262 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by demeter1.kernel.org (8.14.4/8.14.3) with ESMTP id oBDD1kVZ005167 for ; Mon, 13 Dec 2010 13:02:11 GMT Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1757558Ab0LMNCK (ORCPT ); Mon, 13 Dec 2010 08:02:10 -0500 Received: from smtp5-g21.free.fr ([212.27.42.5]:36244 "EHLO smtp5-g21.free.fr" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757498Ab0LMNCJ convert rfc822-to-8bit (ORCPT ); Mon, 13 Dec 2010 08:02:09 -0500 Received: from tele (unknown [82.245.201.222]) by smtp5-g21.free.fr (Postfix) with ESMTP id 2FC58D481D4; Mon, 13 Dec 2010 14:02:02 +0100 (CET) Date: Mon, 13 Dec 2010 14:04:09 +0100 From: Jean-Francois Moine To: Linux Media Mailing List , Mauro Carvalho Chehab Subject: [PATCH 5/6] gspca - sonixj: Add the bit definitions of the bridge reg 0x01 and 0x17 Message-ID: <20101213140409.7e3bc5ab@tele> X-Mailer: Claws Mail 3.7.8 (GTK+ 2.20.1; x86_64-pc-linux-gnu) Mime-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Greylist: IP, sender and recipient auto-whitelisted, not delayed by milter-greylist-4.2.3 (demeter1.kernel.org [140.211.167.41]); Mon, 13 Dec 2010 13:02:12 +0000 (UTC) diff --git a/drivers/media/video/gspca/sonixj.c b/drivers/media/video/gspca/sonixj.c index 9b7e28a..4c10324 100644 --- a/drivers/media/video/gspca/sonixj.c +++ b/drivers/media/video/gspca/sonixj.c @@ -100,6 +100,19 @@ enum sensors { /* device flags */ #define PDN_INV 1 /* inverse pin S_PWR_DN / sn_xxx tables */ +/* sn9c1xx definitions */ +/* register 0x01 */ +#define S_PWR_DN 0x01 /* sensor power down */ +#define S_PDN_INV 0x02 /* inverse pin S_PWR_DN */ +#define V_TX_EN 0x04 /* video transfer enable */ +#define LED 0x08 /* output to pin LED */ +#define SCL_SEL_OD 0x20 /* open-drain mode */ +#define SYS_SEL_48M 0x40 /* system clock 0: 24MHz, 1: 48MHz */ +/* register 0x17 */ +#define MCK_SIZE_MASK 0x1f /* sensor master clock */ +#define SEN_CLK_EN 0x20 /* enable sensor clock */ +#define DEF_EN 0x80 /* defect pixel by 0: soft, 1: hard */ + /* V4L2 controls supported by the driver */ static void setbrightness(struct gspca_dev *gspca_dev); static void setcontrast(struct gspca_dev *gspca_dev);