| Message ID | 20160626210622.5257-3-martin.blumenstingl@googlemail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On 26/06/16 23:06, Martin Blumenstingl wrote: > According to the reference driver (and the datasheet of the newer > Meson8b/S805 and GXBB/S905 SoCs) there are 14 registers, each 32 bit > wide. Then why are you modifying the DTS for the Meson6? As Neil already suggested, it seems that the hardware has been slightly modified for the latest SoCs, so this approach is clearly wrong. Add a new compatible and use of_device_get_match_data() to get the SoC specific data. > Adjust the register size to reflect that, as register offset 0x20 is > now also needed by the meson-ir driver. According to the AML8726-MX (meson6) datasheet the value of 0x20 is correct, at least for that hardware. Cheers,
diff --git a/arch/arm/boot/dts/meson.dtsi b/arch/arm/boot/dts/meson.dtsi index 8c77c87..0f5722a 100644 --- a/arch/arm/boot/dts/meson.dtsi +++ b/arch/arm/boot/dts/meson.dtsi @@ -147,7 +147,7 @@ ir_receiver: ir-receiver@c8100480 { compatible= "amlogic,meson6-ir"; - reg = <0xc8100480 0x20>; + reg = <0xc8100480 0x34>; interrupts = <0 15 1>; status = "disabled"; };
According to the reference driver (and the datasheet of the newer Meson8b/S805 and GXBB/S905 SoCs) there are 14 registers, each 32 bit wide. Adjust the register size to reflect that, as register offset 0x20 is now also needed by the meson-ir driver. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> --- changes in v1 -> v2: - new patch, this is needed because we are now trying to read/write offset 0x20 which is beyond the space which was reserved previously arch/arm/boot/dts/meson.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)