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[37.24.178.151]) by smtp.gmail.com with ESMTPSA id f135sm7441407wmd.7.2017.04.09.12.38.43 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 09 Apr 2017 12:38:43 -0700 (PDT) From: Daniel Scheller To: aospan@netup.ru, serjk@netup.ru, mchehab@kernel.org, linux-media@vger.kernel.org Cc: rjkm@metzlerbros.de Subject: [PATCH 14/19] [media] dvb-frontends/cxd2841er: more configurable TSBITS Date: Sun, 9 Apr 2017 21:38:23 +0200 Message-Id: <20170409193828.18458-15-d.scheller.oss@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170409193828.18458-1-d.scheller.oss@gmail.com> References: <20170409193828.18458-1-d.scheller.oss@gmail.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Scheller Bits 3 and 4 of the TSCONFIG register are important for certain hardware constellations, in that they need to be zeroed. Add a configuration flag to toggle this. Signed-off-by: Daniel Scheller Acked-by: Abylay Ospan --- drivers/media/dvb-frontends/cxd2841er.c | 4 ++++ drivers/media/dvb-frontends/cxd2841er.h | 1 + 2 files changed, 5 insertions(+) diff --git a/drivers/media/dvb-frontends/cxd2841er.c b/drivers/media/dvb-frontends/cxd2841er.c index 67bd13c..efb2795 100644 --- a/drivers/media/dvb-frontends/cxd2841er.c +++ b/drivers/media/dvb-frontends/cxd2841er.c @@ -3794,6 +3794,10 @@ static int cxd2841er_init_tc(struct dvb_frontend *fe) cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, ((priv->flags & CXD2841ER_TS_SERIAL) ? 0x80 : 0x00), 0x80); + /* clear TSCFG bits 3+4 */ + if (priv->flags & CXD2841ER_TSBITS) + cxd2841er_set_reg_bits(priv, I2C_SLVT, 0xc4, 0x00, 0x18); + cxd2841er_init_stats(fe); return 0; diff --git a/drivers/media/dvb-frontends/cxd2841er.h b/drivers/media/dvb-frontends/cxd2841er.h index 4f94422..dc32f5fb 100644 --- a/drivers/media/dvb-frontends/cxd2841er.h +++ b/drivers/media/dvb-frontends/cxd2841er.h @@ -31,6 +31,7 @@ #define CXD2841ER_EARLY_TUNE 16 /* bit 4 */ #define CXD2841ER_NO_WAIT_LOCK 32 /* bit 5 */ #define CXD2841ER_NO_AGCNEG 64 /* bit 6 */ +#define CXD2841ER_TSBITS 128 /* bit 7 */ enum cxd2841er_xtal { SONY_XTAL_20500, /* 20.5 MHz */