From patchwork Sun Apr 9 19:38:25 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Daniel Scheller X-Patchwork-Id: 9671747 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B101E600CB for ; Sun, 9 Apr 2017 19:39:06 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9DA8D26E8A for ; Sun, 9 Apr 2017 19:39:06 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 925BE27F10; Sun, 9 Apr 2017 19:39:06 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.5 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI, RCVD_IN_SORBS_SPAM autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id EA5E026E8A for ; Sun, 9 Apr 2017 19:39:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752665AbdDITjE (ORCPT ); Sun, 9 Apr 2017 15:39:04 -0400 Received: from mail-wm0-f68.google.com ([74.125.82.68]:35470 "EHLO mail-wm0-f68.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752627AbdDITiw (ORCPT ); Sun, 9 Apr 2017 15:38:52 -0400 Received: by mail-wm0-f68.google.com with SMTP id d79so6410945wmi.2 for ; Sun, 09 Apr 2017 12:38:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=scGzbIvFBnZ4owEz+2cfVEi3Im7lqJmgznefxgJeTJ0=; b=prZJ4mmAfMgC9hAbOj3Iy+/b4ZMTQhEi/ksJ2kZdK+7wtfRmFxBaDIpvcEmI5rYKcE 5kPpcwTQnnA6mBLEYID19E6SovuKtWzSywHqGmFSvDsHecC9itQ0TUuLuujEZfBzbl3c whUGJUHrTXd92PTOhx499aZ7YRwzQ2yaXymRRF/xDLiTMhecGXLb861ap6r1ptpFXmnk HE9gLWUGQy+mkKF4XKzWEAKWHIRi+kn7oanEA3Lx9Bx5gUMgPsfb6Id5UEtEuG+mTosE 0cIGJj+R0Yx94nx3rEZ+ugH8XgE2ysO9V1HEJ0J2O7ggauzLG3bBZLyAqvCTGYcG2/Vr W/DA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=scGzbIvFBnZ4owEz+2cfVEi3Im7lqJmgznefxgJeTJ0=; b=GMQyyG0J+ghSlJ7zjkw2uMkQqATIn6qa82rq7hiVUI+Lol0wsbHkPsqJygdVAvNFzu l68XIoalRsAX5ZzsMhwWla/cpKR4BLs7jNsXxnGP5KHQ2paVzR4gQntw92jVJN/xfH0C YruYafwx6SHjVTo5yZz9OyZUHNMWYpyFKjBNVb0oihoSXChYb0n9nx2iM9h+wgIiVWxo Xdi4/YlrLE4b8wNxWEUI20BMWut3Lx2J7x9jQnvnoVFEa8IgEVhuIhb2OL4hpejE3B6H DYaVPOKkj9KmIbt6q4fdoUfWzzqfS63VIauZshdgRttJjVZ3LIigDXus41j3qWsM2XBB YQsw== X-Gm-Message-State: AN3rC/638MirwJzHQJN8yE2fFWZPL/PKkMxBs+vbN0Thkr6x8zRTN/R+ pLhjHzRHIvQaYA== X-Received: by 10.28.157.84 with SMTP id g81mr3565934wme.120.1491766725790; Sun, 09 Apr 2017 12:38:45 -0700 (PDT) Received: from dvbdev.wuest.de (ip-37-24-178-151.hsi14.unitymediagroup.de. [37.24.178.151]) by smtp.gmail.com with ESMTPSA id f135sm7441407wmd.7.2017.04.09.12.38.44 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Sun, 09 Apr 2017 12:38:45 -0700 (PDT) From: Daniel Scheller To: aospan@netup.ru, serjk@netup.ru, mchehab@kernel.org, linux-media@vger.kernel.org Cc: rjkm@metzlerbros.de Subject: [PATCH 16/19] [media] ddbridge: board control setup, ts quirk flags Date: Sun, 9 Apr 2017 21:38:25 +0200 Message-Id: <20170409193828.18458-17-d.scheller.oss@gmail.com> X-Mailer: git-send-email 2.10.2 In-Reply-To: <20170409193828.18458-1-d.scheller.oss@gmail.com> References: <20170409193828.18458-1-d.scheller.oss@gmail.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Daniel Scheller This is a backport of the board control setup from the vendor provided dddvb driver package, which does additional device initialisation based on the board_control device info values. Also backports the TS quirk flags which is used to control setup and usage of the tuner modules soldered on the bridge cards (e.g. CineCTv7, CineS2 V7, MaxA8 and the likes). Functionality originates from ddbridge vendor driver. Permission for reuse and kernel inclusion was formally granted by Ralph Metzler . Cc: Ralph Metzler Signed-off-by: Daniel Scheller --- drivers/media/pci/ddbridge/ddbridge-core.c | 13 +++++++++++++ drivers/media/pci/ddbridge/ddbridge-regs.h | 4 ++++ drivers/media/pci/ddbridge/ddbridge.h | 10 ++++++++++ 3 files changed, 27 insertions(+) diff --git a/drivers/media/pci/ddbridge/ddbridge-core.c b/drivers/media/pci/ddbridge/ddbridge-core.c index 12f5aa3..6b49fa9 100644 --- a/drivers/media/pci/ddbridge/ddbridge-core.c +++ b/drivers/media/pci/ddbridge/ddbridge-core.c @@ -1763,6 +1763,19 @@ static int ddb_probe(struct pci_dev *pdev, const struct pci_device_id *id) ddbwritel(0xfff0f, INTERRUPT_ENABLE); ddbwritel(0, MSI1_ENABLE); + /* board control */ + if (dev->info->board_control) { + ddbwritel(0, DDB_LINK_TAG(0) | BOARD_CONTROL); + msleep(100); + ddbwritel(dev->info->board_control_2, + DDB_LINK_TAG(0) | BOARD_CONTROL); + usleep_range(2000, 3000); + ddbwritel(dev->info->board_control_2 + | dev->info->board_control, + DDB_LINK_TAG(0) | BOARD_CONTROL); + usleep_range(2000, 3000); + } + if (ddb_i2c_init(dev) < 0) goto fail1; ddb_ports_init(dev); diff --git a/drivers/media/pci/ddbridge/ddbridge-regs.h b/drivers/media/pci/ddbridge/ddbridge-regs.h index 6ae8103..98cebb9 100644 --- a/drivers/media/pci/ddbridge/ddbridge-regs.h +++ b/drivers/media/pci/ddbridge/ddbridge-regs.h @@ -34,6 +34,10 @@ /* ------------------------------------------------------------------------- */ +#define BOARD_CONTROL 0x30 + +/* ------------------------------------------------------------------------- */ + /* Interrupt controller */ /* How many MSI's are available depends on HW (Min 2 max 8) */ /* How many are usable also depends on Host platform */ diff --git a/drivers/media/pci/ddbridge/ddbridge.h b/drivers/media/pci/ddbridge/ddbridge.h index 0898f60..734e18e 100644 --- a/drivers/media/pci/ddbridge/ddbridge.h +++ b/drivers/media/pci/ddbridge/ddbridge.h @@ -43,6 +43,10 @@ #define DDB_MAX_PORT 4 #define DDB_MAX_INPUT 8 #define DDB_MAX_OUTPUT 4 +#define DDB_MAX_LINK 4 +#define DDB_LINK_SHIFT 28 + +#define DDB_LINK_TAG(_x) (_x << DDB_LINK_SHIFT) struct ddb_info { int type; @@ -51,6 +55,12 @@ struct ddb_info { char *name; int port_num; u32 port_type[DDB_MAX_PORT]; + u32 board_control; + u32 board_control_2; + u8 ts_quirks; +#define TS_QUIRK_SERIAL 1 +#define TS_QUIRK_REVERSED 2 +#define TS_QUIRK_ALT_OSC 8 }; /* DMA_SIZE MUST be divisible by 188 and 128 !!! */