From patchwork Mon Jun 26 18:12:26 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Laurent Pinchart X-Patchwork-Id: 9810213 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5CD4A60209 for ; Mon, 26 Jun 2017 18:12:53 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5D71328520 for ; Mon, 26 Jun 2017 18:12:53 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5234E285E8; Mon, 26 Jun 2017 18:12:53 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0305428520 for ; Mon, 26 Jun 2017 18:12:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751818AbdFZSMv (ORCPT ); Mon, 26 Jun 2017 14:12:51 -0400 Received: from galahad.ideasonboard.com ([185.26.127.97]:56948 "EHLO galahad.ideasonboard.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751404AbdFZSMu (ORCPT ); Mon, 26 Jun 2017 14:12:50 -0400 Received: from avalon.bb.dnainternet.fi (dfj612ybrt5fhg77mgycy-3.rev.dnainternet.fi [IPv6:2001:14ba:21f5:5b00:2e86:4862:ef6a:2804]) by galahad.ideasonboard.com (Postfix) with ESMTPSA id 7404021441; Mon, 26 Jun 2017 20:12:26 +0200 (CEST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=ideasonboard.com; s=mail; t=1498500746; bh=1BP82jD9p4RCCJDMxTe4/3+MG/VScR5Rs+Dv9Smr2Qo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=GVzESsajEq5uaipGUGe7wjufi+11Qo+U2Uurmbu1wd5EfDnayKhOgA6fjqZ2JXXev RFNgLYQest+YmzIZwQhr1JFb4bVY4MnIZDY24YVEtu79WpN56ceF9zXcynbYZtqmwl GXfO8wnQxNodv9TI/uo/j7dG0styz3Yoc4oGcexA= From: Laurent Pinchart To: dri-devel@lists.freedesktop.org Cc: linux-media@vger.kernel.org, linux-renesas-soc@vger.kernel.org Subject: [PATCH v2 14/14] drm: rcar-du: Configure DPAD0 routing through last group on Gen3 Date: Mon, 26 Jun 2017 21:12:26 +0300 Message-Id: <20170626181226.29575-15-laurent.pinchart+renesas@ideasonboard.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170626181226.29575-1-laurent.pinchart+renesas@ideasonboard.com> References: <20170626181226.29575-1-laurent.pinchart+renesas@ideasonboard.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Gen3 SoCs DPAD0 routing is configured through the last CRTC group, unlike on Gen2 where it is configured through the first CRTC group. Fix the driver accordingly. Fixes: 2427b3037710 ("drm: rcar-du: Add R8A7795 device support") Signed-off-by: Laurent Pinchart --- drivers/gpu/drm/rcar-du/rcar_du_group.c | 21 ++++++++++++++------- 1 file changed, 14 insertions(+), 7 deletions(-) diff --git a/drivers/gpu/drm/rcar-du/rcar_du_group.c b/drivers/gpu/drm/rcar-du/rcar_du_group.c index 64738fca96d0..2abb2fdd143e 100644 --- a/drivers/gpu/drm/rcar-du/rcar_du_group.c +++ b/drivers/gpu/drm/rcar-du/rcar_du_group.c @@ -208,23 +208,30 @@ void rcar_du_group_restart(struct rcar_du_group *rgrp) int rcar_du_set_dpad0_vsp1_routing(struct rcar_du_device *rcdu) { + struct rcar_du_group *rgrp; + struct rcar_du_crtc *crtc; int ret; if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_EXT_CTRL_REGS)) return 0; - /* RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are - * configured in the DEFR8 register of the first group. As this function - * can be called with the DU0 and DU1 CRTCs disabled, we need to enable - * the first group clock before accessing the register. + /* + * RGB output routing to DPAD0 and VSP1D routing to DU0/1/2 are + * configured in the DEFR8 register of the first group on Gen2 and the + * last group on Gen3. As this function can be called with the DU + * channels of the corresponding CRTCs disabled, we need to enable the + * group clock before accessing the register. */ - ret = clk_prepare_enable(rcdu->crtcs[0].clock); + rgrp = &rcdu->groups[DIV_ROUND_UP(rcdu->num_crtcs, 2) - 1]; + crtc = &rcdu->crtcs[rgrp->index * 2]; + + ret = clk_prepare_enable(crtc->clock); if (ret < 0) return ret; - rcar_du_group_setup_defr8(&rcdu->groups[0]); + rcar_du_group_setup_defr8(rgrp); - clk_disable_unprepare(rcdu->crtcs[0].clock); + clk_disable_unprepare(crtc->clock); return 0; }