From patchwork Mon Jul 3 12:40:22 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 9822649 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7045860246 for ; Mon, 3 Jul 2017 12:40:35 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6119827FBA for ; Mon, 3 Jul 2017 12:40:35 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 555C82823E; Mon, 3 Jul 2017 12:40:35 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id ABE2B27FBA for ; Mon, 3 Jul 2017 12:40:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752676AbdGCMkc (ORCPT ); Mon, 3 Jul 2017 08:40:32 -0400 Received: from mail.free-electrons.com ([62.4.15.54]:44621 "EHLO mail.free-electrons.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752065AbdGCMka (ORCPT ); Mon, 3 Jul 2017 08:40:30 -0400 Received: by mail.free-electrons.com (Postfix, from userid 110) id 2ED7E21D4A; Mon, 3 Jul 2017 14:40:27 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.free-electrons.com (Postfix) with ESMTPSA id 02536209B9; Mon, 3 Jul 2017 14:40:26 +0200 (CEST) From: Maxime Ripard To: Mauro Carvalho Chehab , Mark Rutland , Rob Herring Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, Cyprian Wronka , Neil Webb , Richard Sproul , Alan Douglas , Steve Creaney , Thomas Petazzoni , Boris Brezillon , =?UTF-8?q?Niklas=20S=C3=B6derlund?= , Laurent Pinchart , Hans Verkuil , Sakari Ailus , Maxime Ripard Subject: [PATCH 1/2] dt-bindings: media: Add Cadence MIPI-CSI2RX Device Tree bindings Date: Mon, 3 Jul 2017 14:40:22 +0200 Message-Id: <20170703124023.28352-2-maxime.ripard@free-electrons.com> X-Mailer: git-send-email 2.13.0 In-Reply-To: <20170703124023.28352-1-maxime.ripard@free-electrons.com> References: <20170703124023.28352-1-maxime.ripard@free-electrons.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP The Cadence MIPI-CSI2 RX controller is a CSI2RX bridge that supports up to 4 CSI-2 lanes, and can route the frames to up to 4 streams, depending on the hardware implementation. It can operate with an external D-PHY, an internal one or no D-PHY at all in some configurations. Signed-off-by: Maxime Ripard --- .../devicetree/bindings/media/cdns-csi2rx.txt | 87 ++++++++++++++++++++++ 1 file changed, 87 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/cdns-csi2rx.txt diff --git a/Documentation/devicetree/bindings/media/cdns-csi2rx.txt b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt new file mode 100644 index 000000000000..b5bcb6ad18fc --- /dev/null +++ b/Documentation/devicetree/bindings/media/cdns-csi2rx.txt @@ -0,0 +1,87 @@ +Cadence CSI2RX controller +========================= + +The Cadence CSI2RX controller is a CSI-2 bridge supporting up to 4 CSI +lanes in input, and 4 different pixel streams in output. + +Required properties: + - compatible: must be set to "cdns,csi2rx" + - reg: base address and size of the memory mapped region + - clocks: phandles to the clocks driving the controller + - clock-names: must contain: + * sys_clk: main clock + * p_clk: register bank clock + * p_free_clk: free running register bank clock + * pixel_ifX_clk: pixel stream output clock, one for each stream + implemented in hardware, between 0 and 3 + * dphy_rx_clk: D-PHY byte clock, if implemented in hardware + - phys: phandle to the external D-PHY + - phy-names: must contain dphy, if the implementation uses an + external D-PHY + +Required subnodes: + - ports: A ports node with endpoint definitions as defined in + Documentation/devicetree/bindings/media/video-interfaces.txt. The + first port subnode should be the input endpoint, the second one the + outputs + + The output port should have as many endpoints as stream supported by + the hardware implementation, between 1 and 4, their ID being the + stream output number used in the implementation. + +Example: + +csi2rx: csi-bridge@0d060000 { + compatible = "cdns,csi2rx"; + reg = <0x0d060000 0x1000>; + clocks = <&byteclock>, <&byteclock>, <&byteclock>, + <&coreclock>, <&coreclock>, + <&coreclock>, <&coreclock>; + clock-names = "sys_clk", "p_clk", "p_free_clk", + "pixel_if0_clk", "pixel_if1_clk", + "pixel_if2_clk", "pixel_if3_clk"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + #address-cells = <1>; + #size-cells = <0>; + reg = <0>; + + csi2rx_in_sensor: endpoint@0 { + reg = <0>; + remote-endpoint = <&sensor_out_csi2rx>; + clock-lanes = <0>; + data-lanes = <1 2>; + }; + }; + + port@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + + csi2rx_out_grabber0: endpoint@0 { + reg = <0>; + remote-endpoint = <&grabber0_in_csi2rx>; + }; + + csi2rx_out_grabber1: endpoint@1 { + reg = <1>; + remote-endpoint = <&grabber1_in_csi2rx>; + }; + + csi2rx_out_grabber2: endpoint@2 { + reg = <2>; + remote-endpoint = <&grabber2_in_csi2rx>; + }; + + csi2rx_out_grabber3: endpoint@3 { + reg = <3>; + remote-endpoint = <&grabber3_in_csi2rx>; + }; + }; + }; +};