From patchwork Mon Dec 18 14:11:41 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Philipp Rossak X-Patchwork-Id: 10119623 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6631F60327 for ; Mon, 18 Dec 2017 14:14:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 58D8C289E7 for ; Mon, 18 Dec 2017 14:14:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4DBA028C9B; Mon, 18 Dec 2017 14:14:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=2.0 tests=BAYES_00,DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, FREEMAIL_FROM, RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F2585289E7 for ; Mon, 18 Dec 2017 14:14:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758261AbdLRONl (ORCPT ); Mon, 18 Dec 2017 09:13:41 -0500 Received: from mail-wm0-f67.google.com ([74.125.82.67]:42144 "EHLO mail-wm0-f67.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753159AbdLROLw (ORCPT ); Mon, 18 Dec 2017 09:11:52 -0500 Received: by mail-wm0-f67.google.com with SMTP id b199so29590748wme.1; Mon, 18 Dec 2017 06:11:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=b8MEb55PDDl2pZqUsog8UI8eI5rioBonZSzy7NTkKqg=; b=IFzA5rrELOchQOcRwspdCStGBvV+qdxNnFDJv/ZzzdnwQtUL4qapC1YtMEX65OpUhU VfCXFwmn/ynFozC7fB7JgKaljgAKdcwBViFiqzMEBq+5TJcEoeok7APKHJT/MYkDU31Y Rbs4byvzj+piWms/Pbyz6/jOA3wgN0ch5wRRtoI2/hdYocwPIvnzHIguroWnqki2gDeR OMEVwSHh+jUF/z2oJAmPoLBW1U3UAj7pqypLBPdLMoybdTo5CHh9kIcUO3gsEn67cknp 2Q+/TEnFYC3bk9aO8UeO2KxtVHCuZ0T/GilHd38ApAoAd/WRt+91i2/XhOq0SS2ychyT CEcA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=b8MEb55PDDl2pZqUsog8UI8eI5rioBonZSzy7NTkKqg=; b=tfoO4EkqTimj4nGVaceZ7BAp1NRQZ3ZK/RvV0NEXsDdb0zek2hRwfu9W0YvQQmV4kb xGO/0gkjOxOOWGwBhuZIWtS93CcBNlNjvRqFPISDGylN8N/BaIOvJlJ6eOb1O1b14++g SiTQaUjj3Wp1yhwHmwsQ1z4mQKh3he+0yuFZvDauPq5KRI5ofBclhESKdl1AfsZ3VpCK nx3hU6XnbwxUFdQvo9YhJpa79flvuhkCUCo8z9biaf8rzgQy5q2ImDPYRNmmfNtnw91l 5s9Gd6cUuY1M6/Rea8VdqA250wbPKmP2ZR3+HrSZNpS5+6Ytm8Zk1heqbJUT7ylUruNo aD1Q== X-Gm-Message-State: AKGB3mKeVjIwAj08bkfPYCKdMn+av2GzE8HRwyhKr0Gz77liaVIA+8gS PpshyB+0rx14HzPyK0M3Sck= X-Google-Smtp-Source: ACJfBotTXNhZJk426xxZBSIG3+gRUyw55YLrasyoT7Jgom1EH4kHy36bl982BYRaYZLzdJrxQmCiuA== X-Received: by 10.28.235.21 with SMTP id j21mr14974wmh.72.1513606311007; Mon, 18 Dec 2017 06:11:51 -0800 (PST) Received: from debian-laptop.fritz.box (p5B3DDB65.dip0.t-ipconnect.de. [91.61.219.101]) by smtp.gmail.com with ESMTPSA id x127sm5790384wmb.10.2017.12.18.06.11.49 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Mon, 18 Dec 2017 06:11:50 -0800 (PST) From: Philipp Rossak To: mchehab@kernel.org, robh+dt@kernel.org, mark.rutland@arm.com, maxime.ripard@free-electrons.com, wens@csie.org, linux@armlinux.org.uk, sean@mess.org, p.zabel@pengutronix.de, andi.shyti@samsung.com Cc: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 1/6] media: rc: update sunxi-ir driver to get base clock frequency from devicetree Date: Mon, 18 Dec 2017 15:11:41 +0100 Message-Id: <20171218141146.23746-2-embed3d@gmail.com> X-Mailer: git-send-email 2.11.0 In-Reply-To: <20171218141146.23746-1-embed3d@gmail.com> References: <20171218141146.23746-1-embed3d@gmail.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch updates the sunxi-ir driver to set the base clock frequency from devicetree. This is necessary since there are different ir receivers on the market, that operate with different frequencies. So this value could be set if the attached ir receiver needs a different base clock frequency, than the default 8 MHz. Signed-off-by: Philipp Rossak --- drivers/media/rc/sunxi-cir.c | 19 +++++++++++-------- 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/drivers/media/rc/sunxi-cir.c b/drivers/media/rc/sunxi-cir.c index 97f367b446c4..f500cea228a9 100644 --- a/drivers/media/rc/sunxi-cir.c +++ b/drivers/media/rc/sunxi-cir.c @@ -72,12 +72,8 @@ /* CIR_REG register idle threshold */ #define REG_CIR_ITHR(val) (((val) << 8) & (GENMASK(15, 8))) -/* Required frequency for IR0 or IR1 clock in CIR mode */ +/* Required frequency for IR0 or IR1 clock in CIR mode (default) */ #define SUNXI_IR_BASE_CLK 8000000 -/* Frequency after IR internal divider */ -#define SUNXI_IR_CLK (SUNXI_IR_BASE_CLK / 64) -/* Sample period in ns */ -#define SUNXI_IR_SAMPLE (1000000000ul / SUNXI_IR_CLK) /* Noise threshold in samples */ #define SUNXI_IR_RXNOISE 1 /* Idle Threshold in samples */ @@ -122,7 +118,8 @@ static irqreturn_t sunxi_ir_irq(int irqno, void *dev_id) /* for each bit in fifo */ dt = readb(ir->base + SUNXI_IR_RXFIFO_REG); rawir.pulse = (dt & 0x80) != 0; - rawir.duration = ((dt & 0x7f) + 1) * SUNXI_IR_SAMPLE; + rawir.duration = ((dt & 0x7f) + 1) * + ir->rc->rx_resolution; ir_raw_event_store_with_filter(ir->rc, &rawir); } } @@ -148,6 +145,7 @@ static int sunxi_ir_probe(struct platform_device *pdev) struct device_node *dn = dev->of_node; struct resource *res; struct sunxi_ir *ir; + u32 b_clk_freq = SUNXI_IR_BASE_CLK; ir = devm_kzalloc(dev, sizeof(struct sunxi_ir), GFP_KERNEL); if (!ir) @@ -172,6 +170,9 @@ static int sunxi_ir_probe(struct platform_device *pdev) return PTR_ERR(ir->clk); } + /* Base clock frequency (optional) */ + of_property_read_u32(dn, "clock-frequency", &b_clk_freq); + /* Reset (optional) */ ir->rst = devm_reset_control_get_optional_exclusive(dev, NULL); if (IS_ERR(ir->rst)) @@ -180,11 +181,12 @@ static int sunxi_ir_probe(struct platform_device *pdev) if (ret) return ret; - ret = clk_set_rate(ir->clk, SUNXI_IR_BASE_CLK); + ret = clk_set_rate(ir->clk, b_clk_freq); if (ret) { dev_err(dev, "set ir base clock failed!\n"); goto exit_reset_assert; } + dev_dbg(dev, "set base clock frequency to %d Hz.\n", b_clk_freq); if (clk_prepare_enable(ir->apb_clk)) { dev_err(dev, "try to enable apb_ir_clk failed\n"); @@ -225,7 +227,8 @@ static int sunxi_ir_probe(struct platform_device *pdev) ir->rc->map_name = ir->map_name ?: RC_MAP_EMPTY; ir->rc->dev.parent = dev; ir->rc->allowed_protocols = RC_PROTO_BIT_ALL_IR_DECODER; - ir->rc->rx_resolution = SUNXI_IR_SAMPLE; + /* Frequency after IR internal divider with sample period in ns */ + ir->rc->rx_resolution = (1000000000ul / (b_clk_freq / 64)); ir->rc->timeout = MS_TO_NS(SUNXI_IR_TIMEOUT); ir->rc->driver_name = SUNXI_IR_DEV;