From patchwork Fri Mar 9 10:14:42 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 10270341 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 226D960594 for ; Fri, 9 Mar 2018 10:16:52 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0ADD929CE8 for ; Fri, 9 Mar 2018 10:16:52 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id F2CCA29D4D; Fri, 9 Mar 2018 10:16:51 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.9 required=2.0 tests=BAYES_00,RCVD_IN_DNSWL_HI autolearn=unavailable version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A17B729CE8 for ; Fri, 9 Mar 2018 10:16:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751458AbeCIKP4 (ORCPT ); Fri, 9 Mar 2018 05:15:56 -0500 Received: from mail.bootlin.com ([62.4.15.54]:49957 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751056AbeCIKPy (ORCPT ); Fri, 9 Mar 2018 05:15:54 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id 72472207A5; Fri, 9 Mar 2018 11:15:51 +0100 (CET) Received: from localhost.localdomain (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.bootlin.com (Postfix) with ESMTPSA id EDC8420644; Fri, 9 Mar 2018 11:15:50 +0100 (CET) From: Paul Kocialkowski To: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Cc: Icenowy Zheng , Florent Revest , Alexandre Courbot , Hans Verkuil , Laurent Pinchart , Sakari Ailus , Maxime Ripard , Thomas van Kleef , "Signed-off-by : Bob Ham" , Thomas Petazzoni , Chen-Yu Tsai Subject: [PATCH 6/9] sunxi-cedrus: Add device tree binding document Date: Fri, 9 Mar 2018 11:14:42 +0100 Message-Id: <20180309101445.16190-4-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.16.2 In-Reply-To: <20180309100933.15922-3-paul.kocialkowski@bootlin.com> References: <20180309100933.15922-3-paul.kocialkowski@bootlin.com> Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP From: Florent Revest Device Tree bindings for the Allwinner's video engine Signed-off-by: Florent Revest --- .../devicetree/bindings/media/sunxi-cedrus.txt | 44 ++++++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/sunxi-cedrus.txt diff --git a/Documentation/devicetree/bindings/media/sunxi-cedrus.txt b/Documentation/devicetree/bindings/media/sunxi-cedrus.txt new file mode 100644 index 000000000000..138581113c49 --- /dev/null +++ b/Documentation/devicetree/bindings/media/sunxi-cedrus.txt @@ -0,0 +1,44 @@ +Device-Tree bindings for SUNXI video engine found in sunXi SoC family + +Required properties: +- compatible : "allwinner,sun4i-a10-video-engine"; +- memory-region : DMA pool for buffers allocation; +- clocks : list of clock specifiers, corresponding to + entries in clock-names property; +- clock-names : should contain "ahb", "mod" and "ram" entries; +- resets : phandle for reset; +- interrupts : should contain VE interrupt number; +- reg : should contain register base and length of VE. + +Example: + +reserved-memory { + #address-cells = <1>; + #size-cells = <1>; + ranges; + + ve_reserved: cma { + compatible = "shared-dma-pool"; + reg = <0x43d00000 0x9000000>; + no-map; + linux,cma-default; + }; +}; + +video-engine { + compatible = "allwinner,sun4i-a10-video-engine"; + memory-region = <&ve_reserved>; + + clocks = <&ahb_gates 32>, <&ccu CLK_VE>, + <&dram_gates 0>; + clock-names = "ahb", "mod", "ram"; + + assigned-clocks = <&ccu CLK_VE>; + assigned-clock-rates = <320000000>; + + resets = <&ccu RST_VE>; + + interrupts = <53>; + + reg = <0x01c0e000 4096>; +};