| Message ID | 20181114145934.26855-4-maxime.ripard@bootlin.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: sun6i: Add support for the H3 CSI controller | expand |
Hi, On Wed, Nov 14, 2018 at 10:59 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > From: Mylène Josserand <mylene.josserand@bootlin.com> > > The H3 and H5 features the same CSI controller that was initially found on > the A31. > > Add a DT node for it. > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> > --- > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 4b1530ebe427..8779ee750bd8 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -393,6 +393,13 @@ > interrupt-controller; > #interrupt-cells = <3>; > > + csi_pins: csi { > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", You should separate out PE1, which provides the MCLK. Not all camera modules need it. Some might have a standalone crystal to provide the reference clock. Designs could then use that pin for other purposes. Otherwise, Reviewed-by: Chen-Yu Tsai <wens@csie.org> > + "PE5", "PE6", "PE7", "PE8", "PE9", > + "PE10", "PE11"; > + function = "csi"; > + }; > + > emac_rgmii_pins: emac0 { > pins = "PD0", "PD1", "PD2", "PD3", "PD4", > "PD5", "PD7", "PD8", "PD9", "PD10", > @@ -744,6 +751,21 @@ > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + csi: camera@1cb0000 { > + compatible = "allwinner,sun8i-h3-csi", > + "allwinner,sun6i-a31-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; > + resets = <&ccu RST_BUS_CSI>; > + pinctrl-names = "default"; > + pinctrl-0 = <&csi_pins>; > + status = "disabled"; > + }; > + > hdmi: hdmi@1ee0000 { > compatible = "allwinner,sun8i-h3-dw-hdmi", > "allwinner,sun8i-a83t-dw-hdmi"; > -- > 2.19.1 >
On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > From: Mylène Josserand <mylene.josserand@bootlin.com> > > The H3 and H5 features the same CSI controller that was initially found on > the A31. > > Add a DT node for it. > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> > --- > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++ > 1 file changed, 22 insertions(+) > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > index 4b1530ebe427..8779ee750bd8 100644 > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > @@ -393,6 +393,13 @@ > interrupt-controller; > #interrupt-cells = <3>; > > + csi_pins: csi { > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", > + "PE5", "PE6", "PE7", "PE8", "PE9", > + "PE10", "PE11"; > + function = "csi"; > + }; > + > emac_rgmii_pins: emac0 { > pins = "PD0", "PD1", "PD2", "PD3", "PD4", > "PD5", "PD7", "PD8", "PD9", "PD10", > @@ -744,6 +751,21 @@ > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > }; > > + csi: camera@1cb0000 { > + compatible = "allwinner,sun8i-h3-csi", > + "allwinner,sun6i-a31-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; Don't we need CLK_CSI_MCLK which can be pinout via PE1?
On Thu, Nov 22, 2018 at 7:45 PM Jagan Teki <jagan@amarulasolutions.com> wrote: > > On Wed, Nov 14, 2018 at 8:29 PM Maxime Ripard <maxime.ripard@bootlin.com> wrote: > > > > From: Mylène Josserand <mylene.josserand@bootlin.com> > > > > The H3 and H5 features the same CSI controller that was initially found on > > the A31. > > > > Add a DT node for it. > > > > Signed-off-by: Mylène Josserand <mylene.josserand@bootlin.com> > > Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com> > > --- > > arch/arm/boot/dts/sunxi-h3-h5.dtsi | 22 ++++++++++++++++++++++ > > 1 file changed, 22 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > index 4b1530ebe427..8779ee750bd8 100644 > > --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi > > @@ -393,6 +393,13 @@ > > interrupt-controller; > > #interrupt-cells = <3>; > > > > + csi_pins: csi { > > + pins = "PE0", "PE1", "PE2", "PE3", "PE4", > > + "PE5", "PE6", "PE7", "PE8", "PE9", > > + "PE10", "PE11"; > > + function = "csi"; > > + }; > > + > > emac_rgmii_pins: emac0 { > > pins = "PD0", "PD1", "PD2", "PD3", "PD4", > > "PD5", "PD7", "PD8", "PD9", "PD10", > > @@ -744,6 +751,21 @@ > > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; > > > > + csi: camera@1cb0000 { > > + compatible = "allwinner,sun8i-h3-csi", > > + "allwinner,sun6i-a31-csi"; > > + reg = <0x01cb0000 0x1000>; > > + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI_SCLK>, > > + <&ccu CLK_DRAM_CSI>; > > + clock-names = "bus", "mod", "ram"; > > Don't we need CLK_CSI_MCLK which can be pinout via PE1? The CSI hardware block does not have any controls for MCLK. It's simply routed from the CCU directly to the pin. ChenYu
diff --git a/arch/arm/boot/dts/sunxi-h3-h5.dtsi b/arch/arm/boot/dts/sunxi-h3-h5.dtsi index 4b1530ebe427..8779ee750bd8 100644 --- a/arch/arm/boot/dts/sunxi-h3-h5.dtsi +++ b/arch/arm/boot/dts/sunxi-h3-h5.dtsi @@ -393,6 +393,13 @@ interrupt-controller; #interrupt-cells = <3>; + csi_pins: csi { + pins = "PE0", "PE1", "PE2", "PE3", "PE4", + "PE5", "PE6", "PE7", "PE8", "PE9", + "PE10", "PE11"; + function = "csi"; + }; + emac_rgmii_pins: emac0 { pins = "PD0", "PD1", "PD2", "PD3", "PD4", "PD5", "PD7", "PD8", "PD9", "PD10", @@ -744,6 +751,21 @@ interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; }; + csi: camera@1cb0000 { + compatible = "allwinner,sun8i-h3-csi", + "allwinner,sun6i-a31-csi"; + reg = <0x01cb0000 0x1000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ccu CLK_BUS_CSI>, + <&ccu CLK_CSI_SCLK>, + <&ccu CLK_DRAM_CSI>; + clock-names = "bus", "mod", "ram"; + resets = <&ccu RST_BUS_CSI>; + pinctrl-names = "default"; + pinctrl-0 = <&csi_pins>; + status = "disabled"; + }; + hdmi: hdmi@1ee0000 { compatible = "allwinner,sun8i-h3-dw-hdmi", "allwinner,sun8i-a83t-dw-hdmi";