From patchwork Wed Dec 5 09:24:33 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Paul Kocialkowski X-Patchwork-Id: 10713467 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A2E5918B8 for ; Wed, 5 Dec 2018 09:26:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 91C632C905 for ; Wed, 5 Dec 2018 09:26:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8590D2C9AF; Wed, 5 Dec 2018 09:26:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 2A8002C905 for ; Wed, 5 Dec 2018 09:26:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727498AbeLEJZZ (ORCPT ); Wed, 5 Dec 2018 04:25:25 -0500 Received: from mail.bootlin.com ([62.4.15.54]:39787 "EHLO mail.bootlin.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726944AbeLEJZR (ORCPT ); Wed, 5 Dec 2018 04:25:17 -0500 Received: by mail.bootlin.com (Postfix, from userid 110) id CC9D020D23; Wed, 5 Dec 2018 10:25:14 +0100 (CET) Received: from localhost.localdomain (aaubervilliers-681-1-79-44.w90-88.abo.wanadoo.fr [90.88.21.44]) by mail.bootlin.com (Postfix) with ESMTPSA id 6A28220726; Wed, 5 Dec 2018 10:25:04 +0100 (CET) From: Paul Kocialkowski To: linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devel@driverdev.osuosl.org Cc: Mauro Carvalho Chehab , Rob Herring , Mark Rutland , Maxime Ripard , Chen-Yu Tsai , Paul Kocialkowski , Thomas Petazzoni , linux-sunxi@googlegroups.com, Hans Verkuil , Sakari Ailus Subject: [PATCH v2 04/15] soc: sunxi: sram: Enable EMAC clock access for H3 variant Date: Wed, 5 Dec 2018 10:24:33 +0100 Message-Id: <20181205092444.29497-5-paul.kocialkowski@bootlin.com> X-Mailer: git-send-email 2.19.2 In-Reply-To: <20181205092444.29497-1-paul.kocialkowski@bootlin.com> References: <20181205092444.29497-1-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP Just like the A64 and H5, the H3 SoC uses the system control block to enable the EMAC clock. Add a variant structure definition for the H3 and use it over the A10 one. This will allow using the H3-specific binding for the syscon node attached to the EMAC instead of the generic syscon binding. Signed-off-by: Paul Kocialkowski Reviewed-by: Chen-Yu Tsai --- drivers/soc/sunxi/sunxi_sram.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/soc/sunxi/sunxi_sram.c b/drivers/soc/sunxi/sunxi_sram.c index 71e3ee4a3f19..fd81a3c0db45 100644 --- a/drivers/soc/sunxi/sunxi_sram.c +++ b/drivers/soc/sunxi/sunxi_sram.c @@ -290,6 +290,10 @@ static const struct sunxi_sramc_variant sun4i_a10_sramc_variant = { /* Nothing special */ }; +static const struct sunxi_sramc_variant sun8i_h3_sramc_variant = { + .has_emac_clock = true, +}; + static const struct sunxi_sramc_variant sun50i_a64_sramc_variant = { .has_emac_clock = true, }; @@ -369,7 +373,7 @@ static const struct of_device_id sunxi_sram_dt_match[] = { }, { .compatible = "allwinner,sun8i-h3-system-control", - .data = &sun4i_a10_sramc_variant, + .data = &sun8i_h3_sramc_variant, }, { .compatible = "allwinner,sun50i-a64-sram-controller",