From patchwork Sun May 12 06:00:04 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Louis Kuo X-Patchwork-Id: 10939873 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id E5C60924 for ; Sun, 12 May 2019 06:00:29 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D4B1C21F61 for ; Sun, 12 May 2019 06:00:29 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C887623201; Sun, 12 May 2019 06:00:29 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.9 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_HI,UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3237022A2A for ; Sun, 12 May 2019 06:00:28 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726128AbfELGAZ (ORCPT ); Sun, 12 May 2019 02:00:25 -0400 Received: from mailgw01.mediatek.com ([210.61.82.183]:50254 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1725978AbfELGAZ (ORCPT ); Sun, 12 May 2019 02:00:25 -0400 X-UUID: 1e9767c3722943bc873e5a89d9b27950-20190512 X-UUID: 1e9767c3722943bc873e5a89d9b27950-20190512 Received: from mtkcas07.mediatek.inc [(172.21.101.84)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 615525080; Sun, 12 May 2019 14:00:19 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs01n1.mediatek.inc (172.21.101.68) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Sun, 12 May 2019 14:00:17 +0800 Received: from mtkslt306.mediatek.inc (10.21.14.136) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Sun, 12 May 2019 14:00:17 +0800 From: Louis Kuo To: , , , , , CC: , , , , , , , , , , , , , , , Louis Kuo Subject: [RFC PATCH V2 3/4] dt-bindings: mt8183: Add sensor interface dt-bindings Date: Sun, 12 May 2019 14:00:04 +0800 Message-ID: <20190512060005.5444-4-louis.kuo@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20190512060005.5444-1-louis.kuo@mediatek.com> References: <20190512060005.5444-1-louis.kuo@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the DT binding documentation for the sensor interface module in Mediatek SoCs. Signed-off-by: Louis Kuo --- .../bindings/media/mediatek-seninf.txt | 52 +++++++++++++++++++ 1 file changed, 52 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-seninf.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-seninf.txt b/Documentation/devicetree/bindings/media/mediatek-seninf.txt new file mode 100644 index 000000000000..5c84a777acbd --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-seninf.txt @@ -0,0 +1,52 @@ +* Mediatek seninf MIPI-CSI2 host driver + +Seninf MIPI-CSI2 host driver is a HW camera interface controller. It support a widely adopted, +simple, high-speed protocol primarily intended for point-to-point image and video +transmission between cameras and host devices. + +Required properties: + - compatible: "mediatek,mt8183-seninf" + - reg: Must contain an entry for each entry in reg-names. + - reg-names: Must include the following entries: + "base_reg": seninf registers base + "rx_reg": Rx analog registers base + - interrupts: interrupt number to the cpu. + - clocks : clock name from clock manager + - clock-names: must be CLK_CAM_SENINF and CLK_TOP_MUX_SENINF. + It is the clocks of seninf + - port : port for camera sensor + - port reg : must be '0' for camera 0, '1' for camera 1 + - endpoint : config mipi-csi2 port setting for each camera + - data-lanes : the number of the data lane + +Example: + seninf: seninf@1a040000 { + compatible = "mediatek,mt8183_seninf"; + reg = <0 0x1a040000 0 0x8000>, + <0 0x11C80000 0 0x6000>; + reg-names = "base_reg", "ana_reg"; + interrupts = ; + power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>; + clocks = + <&camsys CLK_CAM_SENINF>, <&topckgen CLK_TOP_MUX_SENINF>; + clock-names = + "CLK_CAM_SENINF", "CLK_TOP_MUX_SENINF"; + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + mipi_in_cam0: endpoint@0 { + reg = <0>; + data-lanes = <1 3>; + }; + }; + port@1 { + reg = <1>; + mipi_in_cam1: endpoint@0 { + reg = <1>; + data-lanes = <1 3>; + }; + }; + }; + }