@@ -505,5 +505,35 @@
reg = <0 0x1a000000 0 0x1000>;
#clock-cells = <1>;
};
+ camisp: camisp@1a000000 {
+ compatible = "mediatek,mt8183-camisp";
+ reg = <0 0x1a000000 0 0x1000>,
+ <0 0x1a003000 0 0x1000>,
+ <0 0x1a004000 0 0x2000>,
+ <0 0x1a006000 0 0x2000>,
+ <0 0x1a008000 0 0x2000>;
+ reg-names = "cam_sys",
+ "cam_uni",
+ "cam_a",
+ "cam_b",
+ "cam_c";
+ interrupts = <GIC_SPI 253 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 254 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 255 IRQ_TYPE_LEVEL_LOW>,
+ <GIC_SPI 256 IRQ_TYPE_LEVEL_LOW>;
+ interrupt-names = "cam_uni",
+ "cam_a",
+ "cam_b",
+ "cam_c";
+ iommus = <&iommu M4U_PORT_CAM_IMGO>;
+ clocks = <&camsys CLK_CAM_CAM>,
+ <&camsys CLK_CAM_CAMTG>;
+ clock-names = "camsys_cam_cgpdn",
+ "camsys_camtg_cgpdn";
+ mediatek,larb = <&larb3>,
+ <&larb6>;
+ power-domains = <&scpsys MT8183_POWER_DOMAIN_CAM>;
+ mediatek,scp = <&scp>;
+ };
};
};
Add nodes for Pass 1 unit of Mediatek's camera ISP system. Pass 1 unit embedded in Mediatek SoCs, works with the co-processor to process image signal from the image sensor and output RAW image data. Signed-off-by: Jungo Lin <jungo.lin@mediatek.com> --- arch/arm64/boot/dts/mediatek/mt8183.dtsi | 30 ++++++++++++++++++++++++ 1 file changed, 30 insertions(+)