From patchwork Wed Dec 4 09:44:23 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Xia Jiang X-Patchwork-Id: 11272601 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 32CBD1593 for ; Wed, 4 Dec 2019 09:45:11 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 0E862214AF for ; Wed, 4 Dec 2019 09:45:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="oGxDG09O" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727590AbfLDJpH (ORCPT ); Wed, 4 Dec 2019 04:45:07 -0500 Received: from mailgw02.mediatek.com ([210.61.82.184]:9375 "EHLO mailgw02.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1727477AbfLDJpF (ORCPT ); Wed, 4 Dec 2019 04:45:05 -0500 X-UUID: 528f980957c1488098dbe1f57108914c-20191204 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Transfer-Encoding:Content-Type:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=eI1a1FV+VwSChfULE2XHhJMPkMCeZyf5a8QK8aRHLPE=; b=oGxDG09ONCuOLa40lP5ITQc52Zt3DBu7x8aGd7yINQW/JjAa7DDHOJBQGZKTELDqpUmrG8ff9rue4NprWNXdfeJjUpNCLZo8jwRkNAl12g5vT/LFkNrAXsqZfH2He92WJDoY3A5Ux/r/1TXawD/E5HYbaHOpqkklZ/hhNxlc0Ek=; X-UUID: 528f980957c1488098dbe1f57108914c-20191204 Received: from mtkexhb01.mediatek.inc [(172.21.101.102)] by mailgw02.mediatek.com (envelope-from ) (Cellopoint E-mail Firewall v4.1.10 Build 0809 with TLS) with ESMTP id 427262360; Wed, 04 Dec 2019 17:44:59 +0800 Received: from mtkcas07.mediatek.inc (172.21.101.84) by mtkmbs07n2.mediatek.inc (172.21.101.141) with Microsoft SMTP Server (TLS) id 15.0.1395.4; Wed, 4 Dec 2019 17:44:46 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas07.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1395.4 via Frontend Transport; Wed, 4 Dec 2019 17:44:30 +0800 From: Xia Jiang To: Hans Verkuil , Mauro Carvalho Chehab , Rob Herring , Matthias Brugger , Rick Chang CC: , , , , , Marek Szyprowski , Tomasz Figa , , Xia Jiang Subject: [PATCH v5 2/5] media: dt-bindings: Add jpeg enc device tree node document Date: Wed, 4 Dec 2019 17:44:23 +0800 Message-ID: <20191204094424.2562-3-xia.jiang@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20191204094424.2562-1-xia.jiang@mediatek.com> References: <20191204094424.2562-1-xia.jiang@mediatek.com> MIME-Version: 1.0 X-MTK: N Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add jpeg enc device tree node document Reviewed-by: Rob Herring Signed-off-by: Xia Jiang --- v5: no changes v4: no changes v3: change compatible to SoC specific compatible v2: no changes --- .../bindings/media/mediatek-jpeg-encoder.txt | 37 +++++++++++++++++++ 1 file changed, 37 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt diff --git a/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt new file mode 100644 index 000000000000..fa8da699493b --- /dev/null +++ b/Documentation/devicetree/bindings/media/mediatek-jpeg-encoder.txt @@ -0,0 +1,37 @@ +* MediaTek JPEG Encoder + +MediaTek JPEG Encoder is the JPEG encode hardware present in MediaTek SoCs + +Required properties: +- compatible : should be one of: + "mediatek,mt2701-jpgenc" + ... + followed by "mediatek,mtk-jpgenc" +- reg : physical base address of the JPEG encoder registers and length of + memory mapped region. +- interrupts : interrupt number to the interrupt controller. +- clocks: device clocks, see + Documentation/devicetree/bindings/clock/clock-bindings.txt for details. +- clock-names: must contain "jpgenc". It is the clock of JPEG encoder. +- power-domains: a phandle to the power domain, see + Documentation/devicetree/bindings/power/power_domain.txt for details. +- mediatek,larb: must contain the local arbiters in the current SoCs, see + Documentation/devicetree/bindings/memory-controllers/mediatek,smi-larb.txt + for details. +- iommus: should point to the respective IOMMU block with master port as + argument, see Documentation/devicetree/bindings/iommu/mediatek,iommu.txt + for details. + +Example: + jpegenc: jpegenc@1500a000 { + compatible = "mediatek,mt2701-jpgenc", + "mediatek,mtk-jpgenc"; + reg = <0 0x1500a000 0 0x1000>; + interrupts = ; + clocks = <&imgsys CLK_IMG_VENC>; + clock-names = "jpgenc"; + power-domains = <&scpsys MT2701_POWER_DOMAIN_ISP>; + mediatek,larb = <&larb2>; + iommus = <&iommu MT2701_M4U_PORT_JPGENC_RDMA>, + <&iommu MT2701_M4U_PORT_JPGENC_BSDMA>; + };