From patchwork Sun Dec 15 16:59:17 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Chen-Yu Tsai X-Patchwork-Id: 11292913 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A803B138D for ; Sun, 15 Dec 2019 16:59:57 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8571F24671 for ; Sun, 15 Dec 2019 16:59:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576429197; bh=MFr4r0CtVaXDpNF9mGw8EkkRQEEHSJia0THm3nYQ5t0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:List-ID:From; b=qFYSgzpxiuJBRU3RITHsfKrMEm8qDtLYg2QDLYWrvKPVZb6Qf/Qm649D3vqduySFU kGsyBKy+he9GXsBPaTn5atlvvXzJEos9b4oXOV1FycuEpupSU1nUSUOs8/eyuaIapx +weFOa9eM89X1JSazwqVC8BHPClcqUTyUbyVzWa8= Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1726719AbfLOQ7d (ORCPT ); Sun, 15 Dec 2019 11:59:33 -0500 Received: from mail.kernel.org ([198.145.29.99]:55132 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726530AbfLOQ7c (ORCPT ); Sun, 15 Dec 2019 11:59:32 -0500 Received: from wens.tw (mirror2.csie.ntu.edu.tw [140.112.30.76]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 8E4A724681; Sun, 15 Dec 2019 16:59:31 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1576429171; bh=MFr4r0CtVaXDpNF9mGw8EkkRQEEHSJia0THm3nYQ5t0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=D9ZQd6ZMMz7jiffsSEXfvTw73DPNirugBVvPAUXOy/paHURs42gUWPq9YCCZTyzGE 73uNV3nPw7bbPIHMPyjst+QdtEmUD/DDNyKIglZ0HhFAMrc4/gdXRRGFY8MWK6cvtK F2H83Iyd4O2Vtcw1WBWq4dXJMVFg8Jf+MV/kpmhM= Received: by wens.tw (Postfix, from userid 1000) id 603815FD9D; Mon, 16 Dec 2019 00:59:26 +0800 (CST) From: Chen-Yu Tsai To: Maxime Ripard , Mauro Carvalho Chehab , Sakari Ailus , Rob Herring , Mark Rutland Cc: Chen-Yu Tsai , linux-media@vger.kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Chen-Yu Tsai Subject: [PATCH 07/14] ARM: dts: sun4i: Add CSI1 controller and pinmux options Date: Mon, 16 Dec 2019 00:59:17 +0800 Message-Id: <20191215165924.28314-8-wens@kernel.org> X-Mailer: git-send-email 2.24.0 In-Reply-To: <20191215165924.28314-1-wens@kernel.org> References: <20191215165924.28314-1-wens@kernel.org> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Chen-Yu Tsai The CSI controller driver now supports the second CSI controller, CSI1. Add a device node for it. Pinmuxing options for the MCLK output, the standard 8-bit interface, and a secondary 24-bit interface are included. Signed-off-by: Chen-Yu Tsai --- arch/arm/boot/dts/sun4i-a10.dtsi | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/arm/boot/dts/sun4i-a10.dtsi b/arch/arm/boot/dts/sun4i-a10.dtsi index 4c268b70b735..bf531efc0610 100644 --- a/arch/arm/boot/dts/sun4i-a10.dtsi +++ b/arch/arm/boot/dts/sun4i-a10.dtsi @@ -624,6 +624,16 @@ ohci1: usb@1c1c400 { status = "disabled"; }; + csi1: csi@1c1d000 { + compatible = "allwinner,sun4i-a10-csi1"; + reg = <0x01c1d000 0x1000>; + interrupts = <43>; + clocks = <&ccu CLK_AHB_CSI1>, <&ccu CLK_DRAM_CSI1>; + clock-names = "bus", "ram"; + resets = <&ccu RST_CSI1>; + status = "disabled"; + }; + spi3: spi@1c1f000 { compatible = "allwinner,sun4i-a10-spi"; reg = <0x01c1f000 0x1000>; @@ -670,6 +680,31 @@ can0_ph_pins: can0-ph-pins { function = "can"; }; + /omit-if-no-ref/ + csi1_8bits_pg_pins: csi1-8bits-pg-pins { + pins = "PG0", "PG2", "PG3", "PG4", "PG5", + "PG6", "PG7", "PG8", "PG9", "PG10", + "PG11"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_24bits_ph_pins: csi1-24bits-ph-pins { + pins = "PH0", "PH1", "PH2", "PH3", "PH4", + "PH5", "PH6", "PH7", "PH8", "PH9", + "PH10", "PH11", "PH12", "PH13", "PH14", + "PH15", "PH16", "PH17", "PH18", "PH19", + "PH20", "PH21", "PH22", "PH23", "PH24", + "PH25", "PH26", "PH27"; + function = "csi1"; + }; + + /omit-if-no-ref/ + csi1_clk_pg_pin: csi1-clk-pg-pin { + pins = "PG1"; + function = "csi1"; + }; + emac_pins: emac0-pins { pins = "PA0", "PA1", "PA2", "PA3", "PA4", "PA5", "PA6",