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Tue, 29 Jun 2021 08:21:42 +0000 From: Ming Qian To: mchehab@kernel.org, shawnguo@kernel.org, robh+dt@kernel.org, s.hauer@pengutronix.de Cc: hverkuil-cisco@xs4all.nl, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, aisheng.dong@nxp.com, linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3 01/13] dt-bindings: media: imx8q: add imx video codec bindings Date: Tue, 29 Jun 2021 16:21:02 +0800 Message-Id: <201c608e24da92498fde48708afa2dedde5c8f0b.1624954576.git.ming.qian@nxp.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: References: X-Originating-IP: [119.31.174.70] X-ClientProxiedBy: SG2PR06CA0160.apcprd06.prod.outlook.com (2603:1096:1:1e::14) To AM6PR04MB6341.eurprd04.prod.outlook.com (2603:10a6:20b:d8::14) MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 Received: from lsv11149.swis.cn-sha01.nxp.com (119.31.174.70) by SG2PR06CA0160.apcprd06.prod.outlook.com (2603:1096:1:1e::14) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.4264.19 via Frontend Transport; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: YKQ7thX7CHMMQ1ctMhx+S/n2zZZUxvM0LbipE6aVXOQTzhsB3vPTsZxkTTetVeowxE/FxQ5NGbQcjR/WEPokONGb++BUcRdHo2jPLGMb8TO536wGQUxw1uLlFxUGJ9Zj1Yrwy8RWAI/uu7RfZuXBBqn9QYV0CMKOK7tpQ2ln69uOIT5O7u88+wqFxB0jMYekNeQSK5aUrZI4wJs7eOnVLgAuqnebhbF26F5FyPMYHfuv1V3zFJi9MYL2mYLmwRW+lIwPI1VGZK770aRJLF2vBxcFiLPPKGDN/VSHhfNL5Zdwtwy/diTpa7PY2tZWYZA7224R9hAMyzNw7jv3C7MXgNaPNF1PnZ4ORAR7QqJsYxwar9i1EAv/vLECpMEGDCtmhooxazm+lq2CqulYhMtlG+qLkOlJ9EStuV4xM0P+v26llhVDuTVcT35aJA6VyIGk7AMxRf5+2u6XdSCJSgikgLp6T5ypb803OJgIXqAQwqFwmogw0hEj32azTu2ztAGdME9j5wC/5WVOhub+CgV+K0jFn19H2JmwtwjqB1fwarNwx18cLEoDCcbBGvJ4nLPWj9MPgtRzqDe15uuVOVaepKoxrXaWhljVOEf2j1rEnbjprez/jX6PAm2/lxI+lVBRLtBKsLxDw7UO7SoIIOEsDLSmCnXgZQrQdOiTxQbXH3yslGl2op5X85L1LeVcM+5aIA3l68MVisB81Yvxa8v0glbKViobw2qIPZGlKZKEtx4D5XWexcBAbl6bGo/tIZrx8R0r4BQEQEZfJdHLiiu8vcK1sIl4/y3VFNMjSKRyd+vc3jiDC37jhlEfJbXFjUYUrwHmVwlGLfdjI/0raXuPuY5TXIhMX2rmJ6+Dll0MXYBStQRn5zP53OuKM9pBDc1+3pSj1mAOpuRgvy2iVQxnkhP5/ghqWl10uxzxoSd5krCJFJ/4l+UoNmzkc1hN/veZ7fgk3nKVxIuVorK6K3Bt7HnZQtAOqlPYrIFMaw+W+en6qhmzqUe4MlatGjxdxG6+Fw5Mq1cCdpKPlU++zmXOmduCJDrGaBgtqugbOTX/0zLdHZ3Nrq8+r0/Pn3lHhwwmjp1MvzV+fYT2cckaUCbRaPGWRHHCSquLlj4NKo5t8Us7TDJwZQdrr3n1QG/FTtBmb636kPzxFaq2lQd0MllgT4qvxjp8XVfEsLLDPt8XWN/E4QHqtPa0ErdJOCKrlSDxX4qvGoDOQ8q0EDCqC9ZShtmSOWGuKf87hsJK9AM3xUC66jN0xeXzuz+mS3499372XvcsUFIEwkGnL3v51NlE2N4PoW2uJxBGPdhEcDei5qR7ZwtmDxHOriPOS8Movzgk X-OriginatorOrg: nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: a693a588-3f21-468b-39b5-08d93ad6ed10 X-MS-Exchange-CrossTenant-AuthSource: AM6PR04MB6341.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Jun 2021 08:21:42.5880 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: HafASjxCzhvMt+2+T8IZ8yOZryGj/a3TOGJ740eoS9xUWjszN3bqi2btv+FAyVNxlb5QexoWmJ7J10eFm/c3Jw== X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM6PR04MB4583 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Add devicetree binding documentation for IMX8Q Video Processing Unit IP Signed-off-by: Ming Qian Signed-off-by: Shijie Qin Signed-off-by: Zhou Peng --- .../bindings/media/nxp,imx8q-vpu.yaml | 191 ++++++++++++++++++ 1 file changed, 191 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml diff --git a/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml new file mode 100644 index 000000000000..b9e38caf3d10 --- /dev/null +++ b/Documentation/devicetree/bindings/media/nxp,imx8q-vpu.yaml @@ -0,0 +1,191 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/nxp,imx8q-vpu.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NXP i.MX8Q video encode and decode accelerators + +maintainers: + - Ming Qian + - Shijie Qin + +description: |- + The Amphion MXC video encoder(Windsor) and decoder(Malone) accelerators present + on NXP i.MX8Q SoCs. + +properties: + $nodename: + pattern: "^vpu@[0-9a-f]+$" + + compatible: + oneOf: + - const: nxp,imx8qm-vpu + - const: nxp,imx8qxp-vpu + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + memory-region: + description: + Phandle to a node describing reserved memory used by VPU. + (see bindings/reserved-memory/reserved-memory.txt) + +patternProperties: + "^mailbox@[0-9a-f]+$": + description: + Each vpu encoder or decoder correspond a MU, which used for communication + between driver and firmware. Implement via mailbox on driver. + $ref: ../mailbox/fsl,mu.yaml# + + + "^vpu_core@[0-9a-f]+$": + description: + Each core correspond a decoder or encoder, need to configure them + separately. NXP i.MX8QM SoC has one decoder and two encoder, i.MX8QXP SoC + has one decoder and one encoder. + type: object + + properties: + compatible: + oneOf: + - const: nxp,imx8q-vpu-decoder + - const: nxp,imx8q-vpu-encoder + + reg: + maxItems: 1 + + power-domains: + maxItems: 1 + + mbox-names: + items: + - const: tx0 + - const: tx1 + - const: rx + + mboxes: + description: + List of phandle of 2 MU channels for tx, 1 MU channel for rx. + maxItems: 1 + + nxp,boot-region: + description: + Phandle to a node describing reserved memory used by firmware + loading. + $ref: /schemas/types.yaml#/definitions/phandle + + nxp,rpc-region: + description: + Phandle to a node describing reserved memory used by RPC shared + memory between firmware and driver. + $ref: /schemas/types.yaml#/definitions/phandle + + nxp,print-offset: + description: + The memory offset from RPC address, used by reserve firmware log. + $ref: /schemas/types.yaml#/definitions/uint32 + + required: + - compatible + - reg + - power-domains + - mbox-names + - mboxes + - nxp,boot-region + - nxp,rpc-region + - nxp,print-offset + + additionalProperties: false + +required: + - compatible + - reg + - power-domains + - memory-region + +additionalProperties: true + +examples: + # Device node example for i.MX8QM platform: + - | + #include + + vpu: vpu@2c000000 { + compatible = "nxp,imx8qm-vpu"; + ranges = <0x2c000000 0x2c000000 0x2000000>; + reg = <0x2c000000 0x1000000>; + #address-cells = <1>; + #size-cells = <1>; + power-domains = <&pd IMX_SC_R_VPU>; + memory-region = <&vpu_reserved>; + + mu_m0: mailbox@2d000000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d000000 0x20000>; + interrupts = <0 472 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_0>; + }; + + mu1_m0: mailbox@2d020000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d020000 0x20000>; + interrupts = <0 473 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_1>; + }; + + mu2_m0: mailbox@2d040000 { + compatible = "fsl,imx6sx-mu"; + reg = <0x2d040000 0x20000>; + interrupts = <0 474 4>; + #mbox-cells = <2>; + power-domains = <&pd IMX_SC_R_VPU_MU_2>; + }; + + vpu_core0: vpu_core@2d080000 { + compatible = "nxp,imx8q-vpu-decoder"; + reg = <0x2d080000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_DEC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu_m0 0 0 + &mu_m0 0 1 + &mu_m0 1 0>; + nxp,boot-region = <&decoder_boot>; + nxp,rpc-region = <&decoder_rpc>; + nxp,print-offset = <0x180000>; + }; + + vpu_core1: vpu_core@2d090000 { + compatible = "nxp,imx8q-vpu-encoder"; + reg = <0x2d090000 0x10000>; + power-domains = <&pd IMX_SC_R_VPU_ENC_0>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu1_m0 0 0 + &mu1_m0 0 1 + &mu1_m0 1 0>; + nxp,boot-region = <&encoder1_boot>; + nxp,rpc-region = <&encoder1_rpc>; + nxp,print-offset = <0x80000>; + }; + + vpu_core2: vpu_core@2d0a0000 { + reg = <0x2d0a0000 0x10000>; + compatible = "nxp,imx8q-vpu-encoder"; + power-domains = <&pd IMX_SC_R_VPU_ENC_1>; + mbox-names = "tx0", "tx1", "rx"; + mboxes = <&mu2_m0 0 0 + &mu2_m0 0 1 + &mu2_m0 1 0>; + nxp,boot-region = <&encoder2_boot>; + nxp,rpc-region = <&encoder2_rpc>; + nxp,print-offset = <0x80000>; + }; + }; + +...