| Message ID | 20200125110353.591658-4-jernej.skrabec@siol.net (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | arm64: dts: allwinner: a64: Enable deinterlace core | expand |
Hi, On Sat, Jan 25, 2020 at 12:03:51PM +0100, Jernej Skrabec wrote: > A64 contains MBUS, which is the bus used by DMA devices to access > system memory. > > MBUS controller is responsible for arbitration between channels based > on set priority and can do some other things as well, like report > bandwidth used. It also maps RAM region to different address than CPU. > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > --- > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > index 862b47dc9dc9..d225ea1f3b87 100644 > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > @@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 { > status = "disabled"; > }; > > + mbus: dram-controller@1c62000 { > + compatible = "allwinner,sun50i-a64-mbus"; > + reg = <0x01c62000 0x1000>; > + clocks = <&ccu CLK_MBUS>; We're merging the clock header patch and the DT through two different trees, so you can't use it right away. You should use the raw ID here. (also, as a general remark, it's easier on us to not send the patches during the rc6 <-> rc1 phase), so if you can resend them as soon as rc1 is out, that would be great :) Maxime
Dne ponedeljek, 27. januar 2020 ob 15:59:31 CET je Maxime Ripard napisal(a): > Hi, > > On Sat, Jan 25, 2020 at 12:03:51PM +0100, Jernej Skrabec wrote: > > A64 contains MBUS, which is the bus used by DMA devices to access > > system memory. > > > > MBUS controller is responsible for arbitration between channels based > > on set priority and can do some other things as well, like report > > bandwidth used. It also maps RAM region to different address than CPU. > > > > Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> > > --- > > > > arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ > > 1 file changed, 8 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index > > 862b47dc9dc9..d225ea1f3b87 100644 > > --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi > > @@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 { > > > > status = "disabled"; > > > > }; > > > > + mbus: dram-controller@1c62000 { > > + compatible = "allwinner,sun50i-a64-mbus"; > > + reg = <0x01c62000 0x1000>; > > + clocks = <&ccu CLK_MBUS>; > > We're merging the clock header patch and the DT through two different > trees, so you can't use it right away. You should use the raw ID here. Ok. > > (also, as a general remark, it's easier on us to not send the patches > during the rc6 <-> rc1 phase), so if you can resend them as soon as > rc1 is out, that would be great :) Ok, I'll send v2 then. Best regards, Jernej
diff --git a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi index 862b47dc9dc9..d225ea1f3b87 100644 --- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi +++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi @@ -1061,6 +1061,14 @@ pwm: pwm@1c21400 { status = "disabled"; }; + mbus: dram-controller@1c62000 { + compatible = "allwinner,sun50i-a64-mbus"; + reg = <0x01c62000 0x1000>; + clocks = <&ccu CLK_MBUS>; + dma-ranges = <0x00000000 0x40000000 0xc0000000>; + #interconnect-cells = <1>; + }; + csi: csi@1cb0000 { compatible = "allwinner,sun50i-a64-csi"; reg = <0x01cb0000 0x1000>;
A64 contains MBUS, which is the bus used by DMA devices to access system memory. MBUS controller is responsible for arbitration between channels based on set priority and can do some other things as well, like report bandwidth used. It also maps RAM region to different address than CPU. Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net> --- arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)