| Message ID | 20200320131256.23294-4-p.zabel@pengutronix.de (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add initial i.MX8MQ support | expand |
Hi Shawn, On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote: > Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video > decoder cores and a reset/control block. > > Hook up the bus clock to the VPU power domain to enable handshakes, and > configure the core clocks to 600 MHz and the bus clock to 800 MHz by > default. > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> could you pick up this patch? The driver and binding parts have been merged in media/master. regards Philipp > --- > New in v6. > --- > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++ > 1 file changed, 27 insertions(+) > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > index 6a1e83922c71..98e464ecb68a 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > @@ -666,6 +666,7 @@ > pgc_vpu: power-domain@6 { > #power-domain-cells = <0>; > reg = <IMX8M_POWER_DOMAIN_VPU>; > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > }; > > pgc_disp: power-domain@7 { > @@ -1130,6 +1131,32 @@ > status = "disabled"; > }; > > + vpu: video-codec@38300000 { > + compatible = "nxp,imx8mq-vpu"; > + reg = <0x38300000 0x10000>, > + <0x38310000 0x10000>, > + <0x38320000 0x10000>; > + reg-names = "g1", "g2", "ctrl"; > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-names = "g1", "g2"; > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > + clock-names = "g1", "g2", "bus"; > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > + <&clk IMX8MQ_CLK_VPU_G2>, > + <&clk IMX8MQ_CLK_VPU_BUS>, > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_VPU_PLL_OUT>, > + <&clk IMX8MQ_SYS1_PLL_800M>, > + <&clk IMX8MQ_VPU_PLL>; > + assigned-clock-rates = <600000000>, <600000000>, > + <800000000>, <0>; > + power-domains = <&pgc_vpu>; > + }; > + > pcie0: pcie@33800000 { > compatible = "fsl,imx8mq-pcie"; > reg = <0x33800000 0x400000>,
On Wed, 2020-05-27 at 18:19 +0200, Philipp Zabel wrote: > Hi Shawn, > > On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote: > > Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video > > decoder cores and a reset/control block. > > > > Hook up the bus clock to the VPU power domain to enable handshakes, and > > configure the core clocks to 600 MHz and the bus clock to 800 MHz by > > default. > > > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > > could you pick up this patch? The driver and binding parts have been > merged in media/master. > Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com> Tested-by: Ezequiel Garcia <ezequiel@collabora.com> It looks good and it matches the downstream device tree. Thanks, Ezequiel > regards > Philipp > > > --- > > New in v6. > > --- > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++ > > 1 file changed, 27 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > index 6a1e83922c71..98e464ecb68a 100644 > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > @@ -666,6 +666,7 @@ > > pgc_vpu: power-domain@6 { > > #power-domain-cells = <0>; > > reg = <IMX8M_POWER_DOMAIN_VPU>; > > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > > }; > > > > pgc_disp: power-domain@7 { > > @@ -1130,6 +1131,32 @@ > > status = "disabled"; > > }; > > > > + vpu: video-codec@38300000 { > > + compatible = "nxp,imx8mq-vpu"; > > + reg = <0x38300000 0x10000>, > > + <0x38310000 0x10000>, > > + <0x38320000 0x10000>; > > + reg-names = "g1", "g2", "ctrl"; > > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > > + interrupt-names = "g1", "g2"; > > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > > + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > > + clock-names = "g1", "g2", "bus"; > > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > > + <&clk IMX8MQ_CLK_VPU_G2>, > > + <&clk IMX8MQ_CLK_VPU_BUS>, > > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > > + <&clk IMX8MQ_VPU_PLL_OUT>, > > + <&clk IMX8MQ_SYS1_PLL_800M>, > > + <&clk IMX8MQ_VPU_PLL>; > > + assigned-clock-rates = <600000000>, <600000000>, > > + <800000000>, <0>; > > + power-domains = <&pgc_vpu>; > > + }; > > + > > pcie0: pcie@33800000 { > > compatible = "fsl,imx8mq-pcie"; > > reg = <0x33800000 0x400000>,
Hello Shawn, Gentle ping. Thanks a lot! Ezequiel On Wed, 27 May 2020 at 22:02, Ezequiel Garcia <ezequiel@collabora.com> wrote: > > On Wed, 2020-05-27 at 18:19 +0200, Philipp Zabel wrote: > > Hi Shawn, > > > > On Fri, 2020-03-20 at 14:12 +0100, Philipp Zabel wrote: > > > Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video > > > decoder cores and a reset/control block. > > > > > > Hook up the bus clock to the VPU power domain to enable handshakes, and > > > configure the core clocks to 600 MHz and the bus clock to 800 MHz by > > > default. > > > > > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> > > > > could you pick up this patch? The driver and binding parts have been > > merged in media/master. > > > > Reviewed-by: Ezequiel Garcia <ezequiel@collabora.com> > Tested-by: Ezequiel Garcia <ezequiel@collabora.com> > > It looks good and it matches the downstream device tree. > > Thanks, > Ezequiel > > > regards > > Philipp > > > > > --- > > > New in v6. > > > --- > > > arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++ > > > 1 file changed, 27 insertions(+) > > > > > > diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > > index 6a1e83922c71..98e464ecb68a 100644 > > > --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > > +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi > > > @@ -666,6 +666,7 @@ > > > pgc_vpu: power-domain@6 { > > > #power-domain-cells = <0>; > > > reg = <IMX8M_POWER_DOMAIN_VPU>; > > > + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > > > }; > > > > > > pgc_disp: power-domain@7 { > > > @@ -1130,6 +1131,32 @@ > > > status = "disabled"; > > > }; > > > > > > + vpu: video-codec@38300000 { > > > + compatible = "nxp,imx8mq-vpu"; > > > + reg = <0x38300000 0x10000>, > > > + <0x38310000 0x10000>, > > > + <0x38320000 0x10000>; > > > + reg-names = "g1", "g2", "ctrl"; > > > + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, > > > + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; > > > + interrupt-names = "g1", "g2"; > > > + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, > > > + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, > > > + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; > > > + clock-names = "g1", "g2", "bus"; > > > + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, > > > + <&clk IMX8MQ_CLK_VPU_G2>, > > > + <&clk IMX8MQ_CLK_VPU_BUS>, > > > + <&clk IMX8MQ_VPU_PLL_BYPASS>; > > > + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, > > > + <&clk IMX8MQ_VPU_PLL_OUT>, > > > + <&clk IMX8MQ_SYS1_PLL_800M>, > > > + <&clk IMX8MQ_VPU_PLL>; > > > + assigned-clock-rates = <600000000>, <600000000>, > > > + <800000000>, <0>; > > > + power-domains = <&pgc_vpu>; > > > + }; > > > + > > > pcie0: pcie@33800000 { > > > compatible = "fsl,imx8mq-pcie"; > > > reg = <0x33800000 0x400000>, > >
On Fri, Mar 20, 2020 at 02:12:55PM +0100, Philipp Zabel wrote: > Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video > decoder cores and a reset/control block. > > Hook up the bus clock to the VPU power domain to enable handshakes, and > configure the core clocks to 600 MHz and the bus clock to 800 MHz by > default. > > Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> Applied, thanks.
diff --git a/arch/arm64/boot/dts/freescale/imx8mq.dtsi b/arch/arm64/boot/dts/freescale/imx8mq.dtsi index 6a1e83922c71..98e464ecb68a 100644 --- a/arch/arm64/boot/dts/freescale/imx8mq.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8mq.dtsi @@ -666,6 +666,7 @@ pgc_vpu: power-domain@6 { #power-domain-cells = <0>; reg = <IMX8M_POWER_DOMAIN_VPU>; + clocks = <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; }; pgc_disp: power-domain@7 { @@ -1130,6 +1131,32 @@ status = "disabled"; }; + vpu: video-codec@38300000 { + compatible = "nxp,imx8mq-vpu"; + reg = <0x38300000 0x10000>, + <0x38310000 0x10000>, + <0x38320000 0x10000>; + reg-names = "g1", "g2", "ctrl"; + interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "g1", "g2"; + clocks = <&clk IMX8MQ_CLK_VPU_G1_ROOT>, + <&clk IMX8MQ_CLK_VPU_G2_ROOT>, + <&clk IMX8MQ_CLK_VPU_DEC_ROOT>; + clock-names = "g1", "g2", "bus"; + assigned-clocks = <&clk IMX8MQ_CLK_VPU_G1>, + <&clk IMX8MQ_CLK_VPU_G2>, + <&clk IMX8MQ_CLK_VPU_BUS>, + <&clk IMX8MQ_VPU_PLL_BYPASS>; + assigned-clock-parents = <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_VPU_PLL_OUT>, + <&clk IMX8MQ_SYS1_PLL_800M>, + <&clk IMX8MQ_VPU_PLL>; + assigned-clock-rates = <600000000>, <600000000>, + <800000000>, <0>; + power-domains = <&pgc_vpu>; + }; + pcie0: pcie@33800000 { compatible = "fsl,imx8mq-pcie"; reg = <0x33800000 0x400000>,
Add the i.MX8MQ VPU module which comprises Hantro G1 and G2 video decoder cores and a reset/control block. Hook up the bus clock to the VPU power domain to enable handshakes, and configure the core clocks to 600 MHz and the bus clock to 800 MHz by default. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de> --- New in v6. --- arch/arm64/boot/dts/freescale/imx8mq.dtsi | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+)