@@ -777,10 +777,8 @@ static void csi2_phy_init(struct cal_ctx *ctx)
/* 3.B. Program Stop States */
val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port));
- set_field(&val, CAL_GEN_ENABLE,
- CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
- set_field(&val, CAL_GEN_DISABLE,
- CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
+ set_field(&val, 1, CAL_CSI2_TIMING_STOP_STATE_X16_IO1_MASK);
+ set_field(&val, 0, CAL_CSI2_TIMING_STOP_STATE_X4_IO1_MASK);
set_field(&val, 407, CAL_CSI2_TIMING_STOP_STATE_COUNTER_IO1_MASK);
reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val);
ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Stop States\n",
@@ -789,8 +787,7 @@ static void csi2_phy_init(struct cal_ctx *ctx)
/* 4. Force FORCERXMODE */
val = reg_read(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port));
- set_field(&val, CAL_GEN_ENABLE,
- CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
+ set_field(&val, 1, CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK);
reg_write(ctx->dev, CAL_CSI2_TIMING(ctx->csi2_port), val);
ctx_dbg(3, ctx, "CAL_CSI2_TIMING(%d) = 0x%08x Force RXMODE\n",
ctx->csi2_port,
@@ -849,8 +846,7 @@ static void csi2_wait_for_phy(struct cal_ctx *ctx)
for (i = 0; i < 10; i++) {
if (reg_read_field(ctx->dev,
CAL_CSI2_TIMING(ctx->csi2_port),
- CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) ==
- CAL_GEN_DISABLE)
+ CAL_CSI2_TIMING_FORCE_RX_MODE_IO1_MASK) == 0)
break;
usleep_range(1000, 1100);
}
@@ -944,13 +940,13 @@ static void csi2_ppi_enable(struct cal_ctx *ctx)
{
reg_write(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port), BIT(3));
reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port),
- CAL_GEN_ENABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
+ 1, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
}
static void csi2_ppi_disable(struct cal_ctx *ctx)
{
reg_write_field(ctx->dev, CAL_CSI2_PPI_CTRL(ctx->csi2_port),
- CAL_GEN_DISABLE, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
+ 0, CAL_CSI2_PPI_CTRL_IF_EN_MASK);
}
static void csi2_ctx_config(struct cal_ctx *ctx)
@@ -1025,7 +1021,7 @@ static void pix_proc_config(struct cal_ctx *ctx)
set_field(&val, CAL_PIX_PROC_DPCME_BYPASS, CAL_PIX_PROC_DPCME_MASK);
set_field(&val, pack, CAL_PIX_PROC_PACK_MASK);
set_field(&val, ctx->csi2_port, CAL_PIX_PROC_CPORT_MASK);
- set_field(&val, CAL_GEN_ENABLE, CAL_PIX_PROC_EN_MASK);
+ set_field(&val, 1, CAL_PIX_PROC_EN_MASK);
reg_write(ctx->dev, CAL_PIX_PROC(ctx->csi2_port), val);
ctx_dbg(3, ctx, "CAL_PIX_PROC(%d) = 0x%08x\n", ctx->csi2_port,
reg_read(ctx->dev, CAL_PIX_PROC(ctx->csi2_port)));
@@ -1045,7 +1041,7 @@ static void cal_wr_dma_config(struct cal_ctx *ctx,
CAL_WR_DMA_CTRL_MODE_MASK);
set_field(&val, CAL_WR_DMA_CTRL_PATTERN_LINEAR,
CAL_WR_DMA_CTRL_PATTERN_MASK);
- set_field(&val, CAL_GEN_ENABLE, CAL_WR_DMA_CTRL_STALL_RD_MASK);
+ set_field(&val, 1, CAL_WR_DMA_CTRL_STALL_RD_MASK);
reg_write(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port), val);
ctx_dbg(3, ctx, "CAL_WR_DMA_CTRL(%d) = 0x%08x\n", ctx->csi2_port,
reg_read(ctx->dev, CAL_WR_DMA_CTRL(ctx->csi2_port)));
@@ -100,15 +100,6 @@
/* CAL Control Module Core Camerrx Control register offsets */
#define CM_CTRL_CORE_CAMERRX_CONTROL 0x000
-/*********************************************************************
-* Generic value used in various field below
-*********************************************************************/
-
-#define CAL_GEN_DISABLE 0
-#define CAL_GEN_ENABLE 1
-#define CAL_GEN_FALSE 0
-#define CAL_GEN_TRUE 1
-
/*********************************************************************
* Field Definition Macros
*********************************************************************/