From patchwork Wed Mar 25 12:15:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Tomi Valkeinen X-Patchwork-Id: 11457643 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3A64014B4 for ; Wed, 25 Mar 2020 12:16:26 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 1B0CC2078D for ; Wed, 25 Mar 2020 12:16:26 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="L1TyDCiU" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727540AbgCYMQZ (ORCPT ); Wed, 25 Mar 2020 08:16:25 -0400 Received: from lelv0143.ext.ti.com ([198.47.23.248]:43390 "EHLO lelv0143.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727504AbgCYMQZ (ORCPT ); Wed, 25 Mar 2020 08:16:25 -0400 Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelv0143.ext.ti.com (8.15.2/8.15.2) with ESMTP id 02PCGMU5097395; Wed, 25 Mar 2020 07:16:22 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1585138582; bh=mTv74yiEaU0YhriQaCy7veJwqmkIo3kyyJLZ5sc8Ocw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=L1TyDCiUm541vT+l9ROggnL61bIAhsxHw5FSpxKOs85hDqy1dAk8XFX4OtMG97/vA l//lHZD9Tu7wSIWyPvoIr1QMdPGYOW4f/Lpjowa4c0w25Aanf/vhgWp6jQk40+OqZV RjDhyvxB1mBjszrNecivYJoY7i1mqqhjFuGj4QHo= Received: from DLEE101.ent.ti.com (dlee101.ent.ti.com [157.170.170.31]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 02PCGMH9088093 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Wed, 25 Mar 2020 07:16:22 -0500 Received: from DLEE101.ent.ti.com (157.170.170.31) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3; Wed, 25 Mar 2020 07:16:21 -0500 Received: from lelv0327.itg.ti.com (10.180.67.183) by DLEE101.ent.ti.com (157.170.170.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1847.3 via Frontend Transport; Wed, 25 Mar 2020 07:16:21 -0500 Received: from deskari.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by lelv0327.itg.ti.com (8.15.2/8.15.2) with ESMTP id 02PCFm5G085323; Wed, 25 Mar 2020 07:16:20 -0500 From: Tomi Valkeinen To: , Benoit Parrot , Laurent Pinchart , Hans Verkuil CC: Mauro Carvalho Chehab , Tomi Valkeinen Subject: [PATCH v3 17/19] media: ti-vpe: cal: improve wait for CIO resetdone Date: Wed, 25 Mar 2020 14:15:08 +0200 Message-ID: <20200325121510.25923-18-tomi.valkeinen@ti.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200325121510.25923-1-tomi.valkeinen@ti.com> References: <20200325121510.25923-1-tomi.valkeinen@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Sometimes there is a timeout when waiting for the 'ComplexIO Reset Done'. Testing shows that sometimes we need to wait more than what the current code does. It is not clear how long this wait can be, but it is based on how quickly the sensor provides a valid clock, and how quickly CAL syncs to it. Change the code to make it more obvious how long we'll wait, and set a wider range for usleep_range. Increase the timeout to 750ms. Signed-off-by: Tomi Valkeinen Tested-by: Tomi Valkeinen Reviewed-by: Benoit Parrot --- drivers/media/platform/ti-vpe/cal.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/drivers/media/platform/ti-vpe/cal.c b/drivers/media/platform/ti-vpe/cal.c index e5a319f1fe26..eb8eeb75879d 100644 --- a/drivers/media/platform/ti-vpe/cal.c +++ b/drivers/media/platform/ti-vpe/cal.c @@ -825,15 +825,16 @@ static void csi2_phy_init(struct cal_ctx *ctx) static void csi2_wait_complexio_reset(struct cal_ctx *ctx) { - int i; + unsigned long timeout; - for (i = 0; i < 250; i++) { + timeout = jiffies + msecs_to_jiffies(750); + while (time_before(jiffies, timeout)) { if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port), CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_MASK) == CAL_CSI2_COMPLEXIO_CFG_RESET_DONE_RESETCOMPLETED) break; - usleep_range(1000, 1100); + usleep_range(500, 5000); } if (reg_read_field(ctx->dev, CAL_CSI2_COMPLEXIO_CFG(ctx->csi2_port),