From patchwork Wed Mar 25 17:31:20 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Enric Balletbo i Serra X-Patchwork-Id: 11458361 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 605D41392 for ; Wed, 25 Mar 2020 17:31:46 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 4B6F72078A for ; Wed, 25 Mar 2020 17:31:46 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727795AbgCYRbn (ORCPT ); Wed, 25 Mar 2020 13:31:43 -0400 Received: from bhuna.collabora.co.uk ([46.235.227.227]:37082 "EHLO bhuna.collabora.co.uk" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727129AbgCYRbn (ORCPT ); Wed, 25 Mar 2020 13:31:43 -0400 Received: from [127.0.0.1] (localhost [127.0.0.1]) (Authenticated sender: eballetbo) with ESMTPSA id 10A462969FA From: Enric Balletbo i Serra To: robh+dt@kernel.org, mark.rutland@arm.com, ck.hu@mediatek.com, p.zabel@pengutronix.de, airlied@linux.ie, mturquette@baylibre.com, sboyd@kernel.org, ulrich.hecht+renesas@gmail.com, laurent.pinchart@ideasonboard.com Cc: linux-mediatek@lists.infradead.org, Andrew-CT Chen , rdunlap@infradead.org, frank-w@public-files.de, wens@csie.org, Mauro Carvalho Chehab , Houlong Wei , Collabora Kernel ML , devicetree@vger.kernel.org, Thomas Gleixner , Richard Fontana , Matthias Brugger , Greg Kroah-Hartman , Minghsiu Tsai , matthias.bgg@kernel.org, Allison Randal , linux-kernel@vger.kernel.org, hsinyi@chromium.org, Seiya Wang , linux-clk@vger.kernel.org, mtk01761 , Kate Stewart , Matthias Brugger , sean.wang@mediatek.com, Weiyi Lu , linux-arm-kernel@lists.infradead.org, Daniel Vetter , dri-devel@lists.freedesktop.org, linux-media@vger.kernel.org Subject: [RESEND PATCH v12 2/5] dt-bindings: mediatek: Update mmsys binding to reflect it is a system controller Date: Wed, 25 Mar 2020 18:31:20 +0100 Message-Id: <20200325173123.3569606-3-enric.balletbo@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200325173123.3569606-1-enric.balletbo@collabora.com> References: <20200325173123.3569606-1-enric.balletbo@collabora.com> MIME-Version: 1.0 Sender: linux-media-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org The mmsys system controller is not only a pure clock controller, so update the binding documentation to reflect that apart from providing clocks, it also provides routing and miscellaneous control registers. Signed-off-by: Enric Balletbo i Serra Reviewed-by: Matthias Brugger Reviewed-by: CK Hu --- Changes in v12: None Changes in v10: - Update the binding documentation for the mmsys system controller. Changes in v9: None Changes in v8: None Changes in v7: None .../devicetree/bindings/arm/mediatek/mediatek,mmsys.txt | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt index 301eefbe1618..8d6a9d98e7a6 100644 --- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt +++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.txt @@ -1,7 +1,8 @@ Mediatek mmsys controller ============================ -The Mediatek mmsys controller provides various clocks to the system. +The Mediatek mmsys system controller provides clock control, routing control, +and miscellaneous control in mmsys partition. Required Properties: @@ -15,13 +16,13 @@ Required Properties: - "mediatek,mt8183-mmsys", "syscon" - #clock-cells: Must be 1 -The mmsys controller uses the common clk binding from +For the clock control, the mmsys controller uses the common clk binding from Documentation/devicetree/bindings/clock/clock-bindings.txt The available clocks are defined in dt-bindings/clock/mt*-clk.h. Example: -mmsys: clock-controller@14000000 { +mmsys: syscon@14000000 { compatible = "mediatek,mt8173-mmsys", "syscon"; reg = <0 0x14000000 0 0x1000>; #clock-cells = <1>;