| Message ID | 20200406073017.19462-2-karthik.poduval@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add Rockchip RK3288 support | expand |
Hi Karthik, Thanks for your patch. On 4/6/20 4:30 AM, Karthik Poduval wrote: > add rk3288 support to Rockchip DPHY driver > > tested on tinkerbaord with ov5647 using command > cam -c 1 -C -F cap > > Reported-by: Karthik Poduval <karthik.poduval@gmail.com> As I mentioned in the previous version, this Reported-by tag doesn't make much sense to me here, please check Documentation/process/submitting-patches.rst Same for the other commits in this series. Let me know if you have any question regarding this. > Signed-off-by: Karthik Poduval <karthik.poduval@gmail.com> > --- > .../bindings/phy/rockchip-mipi-dphy-rx0.yaml | 1 + > .../phy-rockchip-dphy-rx0.c | 69 +++++++++++++++++++ > 2 files changed, 70 insertions(+) > > diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > index 5dacece35702..8927c36de532 100644 > --- a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > +++ b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml Please, update bindings in a separated patchset. > @@ -17,6 +17,7 @@ description: | > properties: > compatible: > const: rockchip,rk3399-mipi-dphy-rx0 > + const: rockchip,rk3288-mipi-dphy-rx0 > > reg: > maxItems: 1 > diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c b/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c > index 7c4df6d48c43..36fc1b1ee7ae 100644 > --- a/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c > +++ b/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c > @@ -26,6 +26,15 @@ > #include <linux/platform_device.h> > #include <linux/regmap.h> > > +#define RK3288_GRF_SOC_CON6 0x025c > +#define RK3288_GRF_SOC_CON8 0x0264 > +#define RK3288_GRF_SOC_CON9 0x0268 > +#define RK3288_GRF_SOC_CON10 0x026c > +#define RK3288_GRF_SOC_CON14 0x027c > +#define RK3288_GRF_SOC_STATUS21 0x02d4 > +#define RK3288_GRF_IO_VSEL 0x0380 > +#define RK3288_GRF_SOC_CON15 0x03a4 > + > #define RK3399_GRF_SOC_CON9 0x6224 > #define RK3399_GRF_SOC_CON21 0x6254 > #define RK3399_GRF_SOC_CON22 0x6258 > @@ -47,6 +56,19 @@ struct hsfreq_range { > u8 cfg_bit; > }; > > +static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = { > + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01}, > + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12}, > + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23}, > + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15}, > + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07}, > + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09}, > + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a}, > + { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b}, > + {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c}, > + {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c} > +}; > + > static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { > { 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 }, > { 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 }, > @@ -60,6 +82,11 @@ static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { > { 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c } > }; > > +static const char * const rk3288_mipidphy_clks[] = { > + "dphy-ref", > + "pclk", > +}; clock-names needs to be updated in the bindings as well. Regards, Helen > + > static const char * const rk3399_mipidphy_clks[] = { > "dphy-ref", > "dphy-cfg", > @@ -109,6 +136,36 @@ struct dphy_reg { > #define PHY_REG(_offset, _width, _shift) \ > { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } > > +static const struct dphy_reg rk3288_grf_dphy_regs[] = { > + [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0), > + [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1), > + [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14), > + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0), > + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4), > + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8), > + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0), > + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4), > + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8), > + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12), > + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0), > + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4), > + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8), > + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12), > + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0), > + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1), > + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2), > + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3), > + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12), > + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13), > + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14), > + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15), > + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0), > + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4), > + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8), > + [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1), > + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0), > +}; > + > static const struct dphy_reg rk3399_grf_dphy_regs[] = { > [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0), > [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10), > @@ -303,6 +360,14 @@ static const struct phy_ops rk_dphy_ops = { > .owner = THIS_MODULE, > }; > > +static const struct rk_dphy_drv_data rk3288_mipidphy_drv_data = { > + .clks = rk3288_mipidphy_clks, > + .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks), > + .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges, > + .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges), > + .regs = rk3288_grf_dphy_regs, > +}; > + > static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { > .clks = rk3399_mipidphy_clks, > .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks), > @@ -312,6 +377,10 @@ static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { > }; > > static const struct of_device_id rk_dphy_dt_ids[] = { > + { > + .compatible = "rockchip,rk3288-mipi-dphy-rx0", > + .data = &rk3288_mipidphy_drv_data, > + }, > { > .compatible = "rockchip,rk3399-mipi-dphy-rx0", > .data = &rk3399_mipidphy_drv_data, >
Hey there Karthik, Thanks for your contribution. I'm happy to see this driver is used and tested more. The patch looks good, just some minor comments, in addition to Helen's comments. Hopefully you'll be able to nail this on the v3 :-) It would be really better for us if you could add a cover letter (i.e. PATCH 0/3) in this series. You would be able to put important information there such as testing information, series changelog, so on. See for instance: https://patchwork.linuxtv.org/cover/62830/ Also, please scripts/get_maintainers.pl next time as indication of who to Cc your patches. For instance, I am the author of this driver, but I'm not Cced, so I could have missed your patch. Finally, please put a note at the top of the driver, explaining where the RK3288 support comes from. Something like this would work: "'" RK3288 support based on <file> in <git repo>, branch <b>" """ See below a few more comments. On Mon, 6 Apr 2020 at 04:30, Karthik Poduval <karthik.poduval@gmail.com> wrote: > > add rk3288 support to Rockchip DPHY driver > > tested on tinkerbaord with ov5647 using command > cam -c 1 -C -F cap > Nitpick: s/tinkerbaord/tinkerboard I'd like to have proper sentences in the commit log. This means, sentences start with capital letters and end with a stop. The testing information is normally left for the cover letter. Also, keep in mind you will need to add proper context here: for instance, where does the "cam -c 1 -C -F cap" command come from? I guess it's libcamera, you should mention this. > Reported-by: Karthik Poduval <karthik.poduval@gmail.com> As Helen already pointed out, if you are Reported-by is incorrectly used here. Please read Documentation/process/submitting-patches.rst. Helen mentioned this on the v1. Please make sure you go thru all the feedback you get on each version, before posting a new one. There's no rush :-) > Signed-off-by: Karthik Poduval <karthik.poduval@gmail.com> > --- > .../bindings/phy/rockchip-mipi-dphy-rx0.yaml | 1 + > .../phy-rockchip-dphy-rx0.c | 69 +++++++++++++++++++ > 2 files changed, 70 insertions(+) > > diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > index 5dacece35702..8927c36de532 100644 > --- a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > +++ b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml > @@ -17,6 +17,7 @@ description: | > properties: > compatible: > const: rockchip,rk3399-mipi-dphy-rx0 > + const: rockchip,rk3288-mipi-dphy-rx0 > > reg: > maxItems: 1 > diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c b/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c > index 7c4df6d48c43..36fc1b1ee7ae 100644 > --- a/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c > +++ b/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c > @@ -26,6 +26,15 @@ > #include <linux/platform_device.h> > #include <linux/regmap.h> > > +#define RK3288_GRF_SOC_CON6 0x025c > +#define RK3288_GRF_SOC_CON8 0x0264 > +#define RK3288_GRF_SOC_CON9 0x0268 > +#define RK3288_GRF_SOC_CON10 0x026c > +#define RK3288_GRF_SOC_CON14 0x027c > +#define RK3288_GRF_SOC_STATUS21 0x02d4 > +#define RK3288_GRF_IO_VSEL 0x0380 > +#define RK3288_GRF_SOC_CON15 0x03a4 > + > #define RK3399_GRF_SOC_CON9 0x6224 > #define RK3399_GRF_SOC_CON21 0x6254 > #define RK3399_GRF_SOC_CON22 0x6258 > @@ -47,6 +56,19 @@ struct hsfreq_range { > u8 cfg_bit; > }; > > +static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = { > + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01}, > + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12}, > + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23}, > + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15}, > + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07}, > + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09}, > + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a}, > + { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b}, > + {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c}, > + {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c} > +}; > + > static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { > { 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 }, > { 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 }, > @@ -60,6 +82,11 @@ static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { > { 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c } > }; > > +static const char * const rk3288_mipidphy_clks[] = { > + "dphy-ref", > + "pclk", > +}; > + ... are you sure that you need this pclk? The driver doesn't seem to be accessing any peripheral interface. Can you test without requesting the pclk ? Stay safe! Ezequiel
diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml index 5dacece35702..8927c36de532 100644 --- a/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml +++ b/drivers/staging/media/phy-rockchip-dphy-rx0/Documentation/devicetree/bindings/phy/rockchip-mipi-dphy-rx0.yaml @@ -17,6 +17,7 @@ description: | properties: compatible: const: rockchip,rk3399-mipi-dphy-rx0 + const: rockchip,rk3288-mipi-dphy-rx0 reg: maxItems: 1 diff --git a/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c b/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c index 7c4df6d48c43..36fc1b1ee7ae 100644 --- a/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c +++ b/drivers/staging/media/phy-rockchip-dphy-rx0/phy-rockchip-dphy-rx0.c @@ -26,6 +26,15 @@ #include <linux/platform_device.h> #include <linux/regmap.h> +#define RK3288_GRF_SOC_CON6 0x025c +#define RK3288_GRF_SOC_CON8 0x0264 +#define RK3288_GRF_SOC_CON9 0x0268 +#define RK3288_GRF_SOC_CON10 0x026c +#define RK3288_GRF_SOC_CON14 0x027c +#define RK3288_GRF_SOC_STATUS21 0x02d4 +#define RK3288_GRF_IO_VSEL 0x0380 +#define RK3288_GRF_SOC_CON15 0x03a4 + #define RK3399_GRF_SOC_CON9 0x6224 #define RK3399_GRF_SOC_CON21 0x6254 #define RK3399_GRF_SOC_CON22 0x6258 @@ -47,6 +56,19 @@ struct hsfreq_range { u8 cfg_bit; }; +static const struct hsfreq_range rk3288_mipidphy_hsfreq_ranges[] = { + { 89, 0x00}, { 99, 0x10}, { 109, 0x20}, { 129, 0x01}, + { 139, 0x11}, { 149, 0x21}, { 169, 0x02}, { 179, 0x12}, + { 199, 0x22}, { 219, 0x03}, { 239, 0x13}, { 249, 0x23}, + { 269, 0x04}, { 299, 0x14}, { 329, 0x05}, { 359, 0x15}, + { 399, 0x25}, { 449, 0x06}, { 499, 0x16}, { 549, 0x07}, + { 599, 0x17}, { 649, 0x08}, { 699, 0x18}, { 749, 0x09}, + { 799, 0x19}, { 849, 0x29}, { 899, 0x39}, { 949, 0x0a}, + { 999, 0x1a}, {1049, 0x2a}, {1099, 0x3a}, {1149, 0x0b}, + {1199, 0x1b}, {1249, 0x2b}, {1299, 0x3b}, {1349, 0x0c}, + {1399, 0x1c}, {1449, 0x2c}, {1500, 0x3c} +}; + static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { { 89, 0x00 }, { 99, 0x10 }, { 109, 0x20 }, { 129, 0x01 }, { 139, 0x11 }, { 149, 0x21 }, { 169, 0x02 }, { 179, 0x12 }, @@ -60,6 +82,11 @@ static const struct hsfreq_range rk3399_mipidphy_hsfreq_ranges[] = { { 1399, 0x1c }, { 1449, 0x2c }, { 1500, 0x3c } }; +static const char * const rk3288_mipidphy_clks[] = { + "dphy-ref", + "pclk", +}; + static const char * const rk3399_mipidphy_clks[] = { "dphy-ref", "dphy-cfg", @@ -109,6 +136,36 @@ struct dphy_reg { #define PHY_REG(_offset, _width, _shift) \ { .offset = _offset, .mask = BIT(_width) - 1, .shift = _shift, } +static const struct dphy_reg rk3288_grf_dphy_regs[] = { + [GRF_CON_DISABLE_ISP] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 0), + [GRF_CON_ISP_DPHY_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 1), + [GRF_DSI_CSI_TESTBUS_SEL] = PHY_REG(RK3288_GRF_SOC_CON6, 1, 14), + [GRF_DPHY_TX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 0), + [GRF_DPHY_TX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 4), + [GRF_DPHY_TX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON8, 4, 8), + [GRF_DPHY_TX1RX1_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 0), + [GRF_DPHY_TX1RX1_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 4), + [GRF_DPHY_TX1RX1_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 8), + [GRF_DPHY_TX1RX1_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON9, 4, 12), + [GRF_DPHY_RX0_TURNDISABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 0), + [GRF_DPHY_RX0_FORCERXMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 4), + [GRF_DPHY_RX0_FORCETXSTOPMODE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 8), + [GRF_DPHY_RX0_ENABLE] = PHY_REG(RK3288_GRF_SOC_CON10, 4, 12), + [GRF_DPHY_RX0_TESTCLR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 0), + [GRF_DPHY_RX0_TESTCLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 1), + [GRF_DPHY_RX0_TESTEN] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 2), + [GRF_DPHY_RX0_TESTDIN] = PHY_REG(RK3288_GRF_SOC_CON14, 8, 3), + [GRF_DPHY_TX1RX1_ENABLECLK] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 12), + [GRF_DPHY_RX1_SRC_SEL] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 13), + [GRF_DPHY_TX1RX1_MASTERSLAVEZ] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 14), + [GRF_DPHY_TX1RX1_BASEDIR] = PHY_REG(RK3288_GRF_SOC_CON14, 1, 15), + [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 0), + [GRF_DPHY_TX1RX1_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 4, 4), + [GRF_DPHY_TX0_TURNREQUEST] = PHY_REG(RK3288_GRF_SOC_CON15, 3, 8), + [GRF_DVP_V18SEL] = PHY_REG(RK3288_GRF_IO_VSEL, 1, 1), + [GRF_DPHY_RX0_TESTDOUT] = PHY_REG(RK3288_GRF_SOC_STATUS21, 8, 0), +}; + static const struct dphy_reg rk3399_grf_dphy_regs[] = { [GRF_DPHY_RX0_TURNREQUEST] = PHY_REG(RK3399_GRF_SOC_CON9, 4, 0), [GRF_DPHY_RX0_CLK_INV_SEL] = PHY_REG(RK3399_GRF_SOC_CON9, 1, 10), @@ -303,6 +360,14 @@ static const struct phy_ops rk_dphy_ops = { .owner = THIS_MODULE, }; +static const struct rk_dphy_drv_data rk3288_mipidphy_drv_data = { + .clks = rk3288_mipidphy_clks, + .num_clks = ARRAY_SIZE(rk3288_mipidphy_clks), + .hsfreq_ranges = rk3288_mipidphy_hsfreq_ranges, + .num_hsfreq_ranges = ARRAY_SIZE(rk3288_mipidphy_hsfreq_ranges), + .regs = rk3288_grf_dphy_regs, +}; + static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { .clks = rk3399_mipidphy_clks, .num_clks = ARRAY_SIZE(rk3399_mipidphy_clks), @@ -312,6 +377,10 @@ static const struct rk_dphy_drv_data rk3399_mipidphy_drv_data = { }; static const struct of_device_id rk_dphy_dt_ids[] = { + { + .compatible = "rockchip,rk3288-mipi-dphy-rx0", + .data = &rk3288_mipidphy_drv_data, + }, { .compatible = "rockchip,rk3399-mipi-dphy-rx0", .data = &rk3399_mipidphy_drv_data,
add rk3288 support to Rockchip DPHY driver tested on tinkerbaord with ov5647 using command cam -c 1 -C -F cap Reported-by: Karthik Poduval <karthik.poduval@gmail.com> Signed-off-by: Karthik Poduval <karthik.poduval@gmail.com> --- .../bindings/phy/rockchip-mipi-dphy-rx0.yaml | 1 + .../phy-rockchip-dphy-rx0.c | 69 +++++++++++++++++++ 2 files changed, 70 insertions(+)