From patchwork Fri Sep 25 07:50:29 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 11799315 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 439A16CB for ; Fri, 25 Sep 2020 08:06:04 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 1842623600 for ; Fri, 25 Sep 2020 08:06:04 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=temperror (0-bit key) header.d=phytec.de header.i=@phytec.de header.b="iBv1bbb9" Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727464AbgIYIGD (ORCPT ); Fri, 25 Sep 2020 04:06:03 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:61918 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727450AbgIYIF6 (ORCPT ); Fri, 25 Sep 2020 04:05:58 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a1; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1601020249; x=1603612249; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=W2ZrFbcxd4kDGmQO+BiozH8E+vz+f2nc13eOaGw19XE=; b=iBv1bbb92r0yTpZ1wcrPTdMU0eDJuIRsNLu1ysrjHn9DIrFDPeSZokfc7RDW19Eu nDpGWm12wQTokuRjBp8UN6hyWcwzhHREOPQ0Hv4m9XgdTtgALJd3hAeuUelAQXXz RUv3Xh2aiodZZkIBv6xbTQfQXqd6p/uiQU/28e4tF3o=; X-AuditID: c39127d2-253ff70000001c25-f6-5f6da159bed7 Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 3E.A5.07205.951AD6F5; Fri, 25 Sep 2020 09:50:49 +0200 (CEST) Received: from lws-riedmueller.phytec.de ([172.16.23.108]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2020092509504915-495334 ; Fri, 25 Sep 2020 09:50:49 +0200 From: Stefan Riedmueller To: Laurent Pinchart Cc: Mauro Carvalho Chehab , Sakari Ailus , linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, Dirk Bender , Stefan Riedmueller Subject: [PATCH 5/5] media: mt9p031: Fix corrupted frame after restarting stream Date: Fri, 25 Sep 2020 09:50:29 +0200 Message-Id: <20200925075029.32181-5-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200925075029.32181-1-s.riedmueller@phytec.de> References: <20200925075029.32181-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 25.09.2020 09:50:49, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 25.09.2020 09:50:49 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFlrPLMWRmVeSWpSXmKPExsWyRoCBSzdyYW68we1vchadE5ewW1zeNYfN omfDVlaLZZv+MFl82vKNyYHVY3bHTFaPTas62TzmnQz0+LxJLoAlissmJTUnsyy1SN8ugSvj zptbTAUnRSquH3rN0sDYJtjFyMkhIWAisX/pB0YQW0hgG6PE1W25EPY1Rom7D8tBbDYBI4kF 0xqZQGwRAQuJ3kXTgeq5OJgFnjFKtLe1soEkhAUCJP5Pm8gOYrMIqEqs+3yCBcTmFbCRODDl MBvEMnmJmZe+g9VwCthKHH17nglimY3Eix1/GSHqBSVOznzCArJAQuAKo8TpT7NYIJqFJE4v PssMYjMLaEssW/iaeQKjwCwkPbOQpBYwMq1iFMrNTM5OLcrM1ivIqCxJTdZLSd3ECAzUwxPV L+1g7JvjcYiRiYPxEKMEB7OSCO/xDTnxQrwpiZVVqUX58UWlOanFhxilOViUxHk38JaECQmk J5akZqemFqQWwWSZODilGhgNvl7u+cFwsGfvDN7Z/0z2X1u9n2tH9SqPjyzzcm3OOWb2nkus bSl4mlM0b5Vz9mRBP4/nuxfL/Jv8cIbwvrSgU47TZjp1OLr82mAWGniU+cb9f88UGmy6Y2TM Zj9uNud101635cbUFd7vubLtDM6Xbyn6djVPW6ugV/bTmsOL+M/L+eh3lfxWYinOSDTUYi4q TgQA/2/8F0ICAAA= Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dirk Bender To prevent corrupted frames after starting and stopping the sensor it's datasheet specifies a specific pause sequence to follow: Stopping: Set Pause_Restart Bit -> Set Restart Bit -> Set Chip_Enable Off Restarting: Set Chip_Enable On -> Clear Pause_Restart Bit The Restart Bit is cleared automatically and must not be cleared manually as this would cause undefined behavior. Signed-off-by: Dirk Bender Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 8f8ee37a2dd2..2f2daf95dcd3 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -80,6 +80,8 @@ #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) #define MT9P031_FRAME_RESTART 0x0b +#define MT9P031_FRAME_RESTART_SET (1 << 0) +#define MT9P031_FRAME_PAUSE_RESTART_SET (1 << 1) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d #define MT9P031_RST_ENABLE 1 @@ -483,9 +485,25 @@ static int mt9p031_set_params(struct mt9p031 *mt9p031) static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) { struct mt9p031 *mt9p031 = to_mt9p031(subdev); + struct i2c_client *client = v4l2_get_subdevdata(subdev); + int val; int ret; if (!enable) { + val = mt9p031_read(client, MT9P031_FRAME_RESTART); + + /* enable pause restart */ + val |= MT9P031_FRAME_PAUSE_RESTART_SET; + ret = mt9p031_write(client, MT9P031_FRAME_RESTART, val); + if (ret < 0) + return ret; + + /* enable restart + keep pause restart set */ + val |= MT9P031_FRAME_RESTART_SET; + ret = mt9p031_write(client, MT9P031_FRAME_RESTART, val); + if (ret < 0) + return ret; + /* Stop sensor readout */ ret = mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); @@ -505,6 +523,13 @@ static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) if (ret < 0) return ret; + val = mt9p031_read(client, MT9P031_FRAME_RESTART); + /* disable reset + pause restart */ + val &= ~MT9P031_FRAME_PAUSE_RESTART_SET; + ret = mt9p031_write(client, MT9P031_FRAME_RESTART, val); + if (ret < 0) + return ret; + return mt9p031_pll_enable(mt9p031); }