From patchwork Wed Sep 30 15:28:16 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sakari Ailus X-Patchwork-Id: 11809471 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 5CF0E92C for ; Wed, 30 Sep 2020 15:29:14 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 48E0F20789 for ; Wed, 30 Sep 2020 15:29:14 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1731032AbgI3P3N (ORCPT ); Wed, 30 Sep 2020 11:29:13 -0400 Received: from retiisi.org.uk ([95.216.213.190]:44650 "EHLO hillosipuli.retiisi.eu" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1731005AbgI3P3L (ORCPT ); Wed, 30 Sep 2020 11:29:11 -0400 Received: from lanttu.localdomain (lanttu-e.localdomain [192.168.1.64]) by hillosipuli.retiisi.eu (Postfix) with ESMTP id 68462634CE1 for ; Wed, 30 Sep 2020 18:28:51 +0300 (EEST) From: Sakari Ailus To: linux-media@vger.kernel.org Subject: [PATCH 058/100] ccs-pll: Use the BIT macro Date: Wed, 30 Sep 2020 18:28:16 +0300 Message-Id: <20200930152858.8471-59-sakari.ailus@linux.intel.com> X-Mailer: git-send-email 2.27.0 In-Reply-To: <20200930152858.8471-1-sakari.ailus@linux.intel.com> References: <20200930152858.8471-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Use the BIT macro for setting individual bits. Signed-off-by: Sakari Ailus --- drivers/media/i2c/ccs-pll.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/media/i2c/ccs-pll.h b/drivers/media/i2c/ccs-pll.h index e01359f61476..f772ed8ef579 100644 --- a/drivers/media/i2c/ccs-pll.h +++ b/drivers/media/i2c/ccs-pll.h @@ -12,13 +12,16 @@ #ifndef CCS_PLL_H #define CCS_PLL_H +#include + /* CSI-2 or CCP-2 */ #define CCS_PLL_BUS_TYPE_CSI2_DPHY 0x00 #define CCS_PLL_BUS_TYPE_CSI2_CPHY 0x01 +/* Old SMIA and implementation specific flags */ /* op pix clock is for all lanes in total normally */ -#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE (1 << 0) -#define CCS_PLL_FLAG_NO_OP_CLOCKS (1 << 1) +#define CCS_PLL_FLAG_OP_PIX_CLOCK_PER_LANE BIT(0) +#define CCS_PLL_FLAG_NO_OP_CLOCKS BIT(1) /** * struct ccs_pll_branch_fr - CCS PLL configuration (front)