| Message ID | 20201102030821.3049-4-mirela.rabulea@oss.nxp.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Add V4L2 driver for i.MX8 JPEG Encoder/Decoder | expand |
On Mon, Nov 02, 2020 at 05:08:13AM +0200, Mirela Rabulea (OSS) wrote: > From: Mirela Rabulea <mirela.rabulea@nxp.com> > > Add bindings documentation for i.MX8QXP/QM JPEG decoder & encoder driver. > > Signed-off-by: Mirela Rabulea <mirela.rabulea@nxp.com> > --- > .../devicetree/bindings/media/imx8-jpeg.yaml | 83 +++++++++++++++++++ > 1 file changed, 83 insertions(+) > create mode 100644 Documentation/devicetree/bindings/media/imx8-jpeg.yaml > > diff --git a/Documentation/devicetree/bindings/media/imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/imx8-jpeg.yaml > new file mode 100644 > index 000000000000..2df538d87bfd > --- /dev/null > +++ b/Documentation/devicetree/bindings/media/imx8-jpeg.yaml > @@ -0,0 +1,83 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/media/imx8-jpeg.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings > + > +maintainers: > + - Mirela Rabulea <mirela.rabulea@nxp.com> > + > +description: |- > + The JPEG decoder/encoder present in.MXQXP/QM SoC is an > + ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline > + and Extended Sequential DCT modes. > + > +properties: > + compatible: > + items: > + - enum: > + # JPEG decoder > + - fsl,imx8-jpgdec > + # JPEG encoder > + - fsl,imx8-jpgenc Which imx8? Should be SoC specific. > + > + reg: > + maxItems: 1 > + > + interrupts: > + description: | > + There are 4 slots available in the IP > + If a certain slot is used, it should have an associated interrupt > + minItems: 1 # At least one slot should be available > + maxItems: 4 # The IP has 4 slots available for use You don't need to know which slot is available? > + > + power-domains: > + description: > + List of phandle and PM domain specifier as documented in > + Documentation/devicetree/bindings/power/power_domain.txt > + minItems: 2 # Wrapper and 1 slot > + maxItems: 5 # Wrapper and 4 slots > + > +required: > + - compatible > + - reg > + - interrupts > + - power-domains > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/firmware/imx/rsrc.h> > + > + jpegdec: jpegdec@58400000 { > + compatible = "fsl,imx8-jpgdec"; > + reg = <0x58400000 0x00050000 >; > + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, > + <&pd IMX_SC_R_MJPEG_DEC_S0>, > + <&pd IMX_SC_R_MJPEG_DEC_S1>, > + <&pd IMX_SC_R_MJPEG_DEC_S2>, > + <&pd IMX_SC_R_MJPEG_DEC_S3>; > + }; > + > + jpegenc: jpegenc@58450000 { > + compatible = "fsl,imx8-jpgenc"; > + reg = <0x58450000 0x00050000 >; > + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, > + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; > + power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, > + <&pd IMX_SC_R_MJPEG_ENC_S0>, > + <&pd IMX_SC_R_MJPEG_ENC_S1>, > + <&pd IMX_SC_R_MJPEG_ENC_S2>, > + <&pd IMX_SC_R_MJPEG_ENC_S3>; > + }; > +... > -- > 2.17.1 >
Hi, On Wed, 2020-11-04 at 16:38 -0600, Rob Herring wrote: > > +title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings > > + > > +maintainers: > > + - Mirela Rabulea <mirela.rabulea@nxp.com> > > + > > +description: |- > > + The JPEG decoder/encoder present in.MXQXP/QM SoC is an > > + ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for > > Baseline > > + and Extended Sequential DCT modes. > > + > > +properties: > > + compatible: > > + items: > > + - enum: > > + # JPEG decoder > > + - fsl,imx8-jpgdec > > + # JPEG encoder > > + - fsl,imx8-jpgenc > > Which imx8? Should be SoC specific. This IP is present in 2 SOCs, imx8qxp & imx8qm. For the next version, I modified the compatibles to nxp,imx8qxp-jpgdec & nxp,imx8qxp-jpgenc, since only 8qxp was tested upstream. I kept the name of the yaml file generic, but modified it to nxp,imx8- jpeg.yaml. Possibly, in the future, this file will also host imx8qm compatibles. Also changed the dtb & driver accordingly. > > > + > > + reg: > > + maxItems: 1 > > + > > + interrupts: > > + description: | > > + There are 4 slots available in the IP > > + If a certain slot is used, it should have an associated > > interrupt > > + minItems: 1 # At least one slot should be > > available > > + maxItems: 4 # The IP has 4 slots available for > > use > > You don't need to know which slot is available? No, the driver keeps track of which slots are used (and, for now, only uses slot 0). It is also possible to determine which is the current running slot by accessing a status memory mapped register (the IP runs the configured slots in a round-robin manner, not in parallel). The assumption is, however, that in the device node, the interrupt i is for slot i. So, I rephrased this to: interrupts: description: | There are 4 slots available in the IP, which the driver may use If a certain slot is used, it should have an associated interrupt The interrupt with index i is assumed to be for slot i minItems: 1 # At least one slot is needed by the driver maxItems: 4 # The IP has 4 slots available for use Thanks, Mirela
diff --git a/Documentation/devicetree/bindings/media/imx8-jpeg.yaml b/Documentation/devicetree/bindings/media/imx8-jpeg.yaml new file mode 100644 index 000000000000..2df538d87bfd --- /dev/null +++ b/Documentation/devicetree/bindings/media/imx8-jpeg.yaml @@ -0,0 +1,83 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/imx8-jpeg.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings + +maintainers: + - Mirela Rabulea <mirela.rabulea@nxp.com> + +description: |- + The JPEG decoder/encoder present in.MXQXP/QM SoC is an + ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline + and Extended Sequential DCT modes. + +properties: + compatible: + items: + - enum: + # JPEG decoder + - fsl,imx8-jpgdec + # JPEG encoder + - fsl,imx8-jpgenc + + reg: + maxItems: 1 + + interrupts: + description: | + There are 4 slots available in the IP + If a certain slot is used, it should have an associated interrupt + minItems: 1 # At least one slot should be available + maxItems: 4 # The IP has 4 slots available for use + + power-domains: + description: + List of phandle and PM domain specifier as documented in + Documentation/devicetree/bindings/power/power_domain.txt + minItems: 2 # Wrapper and 1 slot + maxItems: 5 # Wrapper and 4 slots + +required: + - compatible + - reg + - interrupts + - power-domains + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/firmware/imx/rsrc.h> + + jpegdec: jpegdec@58400000 { + compatible = "fsl,imx8-jpgdec"; + reg = <0x58400000 0x00050000 >; + interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>, + <&pd IMX_SC_R_MJPEG_DEC_S0>, + <&pd IMX_SC_R_MJPEG_DEC_S1>, + <&pd IMX_SC_R_MJPEG_DEC_S2>, + <&pd IMX_SC_R_MJPEG_DEC_S3>; + }; + + jpegenc: jpegenc@58450000 { + compatible = "fsl,imx8-jpgenc"; + reg = <0x58450000 0x00050000 >; + interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>; + power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>, + <&pd IMX_SC_R_MJPEG_ENC_S0>, + <&pd IMX_SC_R_MJPEG_ENC_S1>, + <&pd IMX_SC_R_MJPEG_ENC_S2>, + <&pd IMX_SC_R_MJPEG_ENC_S3>; + }; +...