| Message ID | 20201104234427.26477-6-digetx@gmail.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | Introduce core voltage scaling for NVIDIA Tegra20/30 SoCs | expand |
On Thu, 05 Nov 2020 02:44:02 +0300, Dmitry Osipenko wrote: > Document new OPP table and NVIDIA Tegra-specific voltage regulator > properties. > > Signed-off-by: Dmitry Osipenko <digetx@gmail.com> > --- > Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 4 ++++ > 1 file changed, 4 insertions(+) > Reviewed-by: Rob Herring <robh@kernel.org>
diff --git a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt index a5c5db6a0b2d..f02a98201062 100644 --- a/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt +++ b/Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt @@ -90,6 +90,7 @@ Optional properties: case, the "idle" state needs to pull down the data and strobe pin and the "active" state needs to pull up the strobe pin. - pinctrl-n: alternate pin modes +- operating-points-v2: See ../bindings/opp/opp.txt for details. i.mx specific properties - fsl,usbmisc: phandler of non-core register device, with one @@ -110,6 +111,9 @@ i.mx specific properties The range is from 0x0 to 0xf, the default value is 0x3. Details can refer to TXVREFTUNE0 bits of USBNC_n_PHY_CFG1. +Tegra specific properties +- core-supply: phandle of voltage regulator of the SoC "core" power domain + Example: usb@f7ed0000 {
Document new OPP table and NVIDIA Tegra-specific voltage regulator properties. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> --- Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt | 4 ++++ 1 file changed, 4 insertions(+)