[17/38] ccs: Add support for lane speed model

Message ID	20201202180641.17401-18-sakari.ailus@linux.intel.com (mailing list archive)
State	New, archived
Headers	show Return-Path: <linux-media-owner@kernel.org> From: Sakari Ailus <sakari.ailus@linux.intel.com> To: linux-media@vger.kernel.org Cc: mchehab@kernel.org Subject: [PATCH 17/38] ccs: Add support for lane speed model Date: Wed, 2 Dec 2020 20:06:20 +0200 Message-Id: <20201202180641.17401-18-sakari.ailus@linux.intel.com> In-Reply-To: <20201202180641.17401-1-sakari.ailus@linux.intel.com> References: <20201202180641.17401-1-sakari.ailus@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk
Series	Support additional CCS PLL features, C-PHY \| expand [00/38] Support additional CCS PLL features, C-PHY [01/38] ccs-pll: Don't use div_u64 to divide a 32-bit number [02/38] ccs-pll: Split limits and PLL configuration into front and back parts [03/38] ccs-pll: Use correct VT divisor for calculating VT SYS divisor [04/38] ccs-pll: End search if there are no better values available [05/38] ccs-pll: Remove parallel bus support [06/38] ccs-pll: Differentiate between CSI-2 D-PHY and C-PHY [07/38] ccs-pll: Move the flags field down, away from 8-bit fields [08/38] ccs-pll: Document the structs in the header as well as the function [09/38] ccs-pll: Use the BIT macro [10/38] ccs-pll: Begin calculation from OP system clock frequency [11/38] ccs-pll: Fix condition for pre-PLL divider lower bound [12/38] ccs-pll: Avoid overflow in pre-PLL divisor lower bound search [13/38] ccs-pll: Fix comment on check against maximum PLL multiplier [14/38] ccs-pll: Fix check for PLL multiplier upper bound [15/38] ccs-pll: Use explicit 32-bit unsigned type [16/38] ccs-pll: Add support for lane speed model [17/38] ccs: Add support for lane speed model [18/38] ccs-pll: Add support for decoupled OP domain calculation [19/38] ccs-pll: Add support for extended input PLL clock divider [20/38] ccs-pll: Support two cycles per pixel on OP domain [21/38] ccs-pll: Add support flexible OP PLL pixel clock divider [22/38] ccs-pll: Add sanity checks [23/38] ccs-pll: Add C-PHY support [24/38] ccs-pll: Split off VT subtree calculation [25/38] ccs-pll: Check for derating and overrating, support non-derating sensors [26/38] ccs-pll: Better separate OP and VT sub-tree calculation [27/38] ccs-pll: Print relevant information on PLL tree [28/38] ccs-pll: Rework bounds checks [29/38] ccs-pll: Make VT divisors 16-bit [30/38] ccs-pll: Fix VT post-PLL divisor calculation [31/38] ccs-pll: Separate VT divisor limit calculation from the rest [32/38] ccs-pll: Add trivial dual PLL support [33/38] ccs: Dual PLL support [34/38] ccs-pll: Add support for DDR OP system and pixel clocks [35/38] ccs: Add support for DDR OP SYS and OP PIX clocks [36/38] ccs: Print written register values [37/38] ccs-pll: Print pixel rates [38/38] ccs: Add support for obtaining C-PHY configuration from firmware

Message ID

20201202180641.17401-18-sakari.ailus@linux.intel.com (mailing list archive)

State

New, archived

Headers

From: Sakari Ailus <sakari.ailus@linux.intel.com>
To: linux-media@vger.kernel.org
Cc: mchehab@kernel.org
Subject: [PATCH 17/38] ccs: Add support for lane speed model
Date: Wed,  2 Dec 2020 20:06:20 +0200
Message-Id: <20201202180641.17401-18-sakari.ailus@linux.intel.com>
In-Reply-To: <20201202180641.17401-1-sakari.ailus@linux.intel.com>
References: <20201202180641.17401-1-sakari.ailus@linux.intel.com>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Precedence: bulk

Series

Support additional CCS PLL features, C-PHY | expand

Commit Message

Sakari Ailus Dec. 2, 2020, 6:06 p.m. UTC

Convey the relevant PLL flags to the PLL calculator. Also the lane speed
model affects how the link rate is calculated on the CSI-2 bus, as the
rate is total of all lanes.

Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
---
 drivers/media/i2c/ccs/ccs-core.c | 11 ++++++++++-
 1 file changed, 10 insertions(+), 1 deletion(-)

diff --git a/drivers/media/i2c/ccs/ccs-core.c b/drivers/media/i2c/ccs/ccs-core.c
index 591953cec6ec..f3d4209c818c 100644
--- a/drivers/media/i2c/ccs/ccs-core.c
+++ b/drivers/media/i2c/ccs/ccs-core.c
@@ -387,7 +387,9 @@  static int ccs_pll_configure(struct ccs_sensor *sensor)
 	/* Lane op clock ratio does not apply here. */
 	rval = ccs_write(sensor, REQUESTED_LINK_RATE,
 			 DIV_ROUND_UP(pll->op_bk.sys_clk_freq_hz,
-				      1000000 / 256 / 256));
+				      1000000 / 256 / 256) *
+			 (pll->flags & CCS_PLL_FLAG_LANE_SPEED_MODEL ?
+			  sensor->pll.csi2.lanes : 1));
 	if (rval < 0 || sensor->pll.flags & CCS_PLL_FLAG_NO_OP_CLOCKS)
 		return rval;
 
@@ -3203,6 +3205,13 @@  static int ccs_probe(struct i2c_client *client)
 	/* prepare PLL configuration input values */
 	sensor->pll.bus_type = CCS_PLL_BUS_TYPE_CSI2_DPHY;
 	sensor->pll.csi2.lanes = sensor->hwcfg.lanes;
+	if (CCS_LIM(sensor, CLOCK_CALCULATION) &
+	    CCS_CLOCK_CALCULATION_LANE_SPEED) {
+		sensor->pll.vt_lanes =
+			CCS_LIM(sensor, NUM_OF_VT_LANES) + 1;
+		sensor->pll.op_lanes = sensor->pll.vt_lanes;
+		sensor->pll.flags |= CCS_PLL_FLAG_LANE_SPEED_MODEL;
+	}
 	sensor->pll.ext_clk_freq_hz = sensor->hwcfg.ext_clk;
 	sensor->pll.scale_n = CCS_LIM(sensor, SCALER_N_MIN);

[17/38] ccs: Add support for lane speed model

Commit Message

Patch