From patchwork Wed Mar 3 11:39:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benjamin Gaignard X-Patchwork-Id: 12113411 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id D609FC43332 for ; Wed, 3 Mar 2021 12:57:43 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id A4B5664E58 for ; Wed, 3 Mar 2021 12:57:43 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1443524AbhCCMOs (ORCPT ); Wed, 3 Mar 2021 07:14:48 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55934 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243218AbhCCLqR (ORCPT ); Wed, 3 Mar 2021 06:46:17 -0500 Received: from bhuna.collabora.co.uk (bhuna.collabora.co.uk [IPv6:2a00:1098:0:82:1000:25:2eeb:e3e3]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 34126C061224; Wed, 3 Mar 2021 03:45:26 -0800 (PST) Received: from localhost.localdomain (unknown [IPv6:2a01:e0a:4cb:a870:2035:1dcd:21c7:b3af]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: benjamin.gaignard) by bhuna.collabora.co.uk (Postfix) with ESMTPSA id ACD681F45C2D; Wed, 3 Mar 2021 11:40:21 +0000 (GMT) From: Benjamin Gaignard To: ezequiel@collabora.com, p.zabel@pengutronix.de, mchehab@kernel.org, robh+dt@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, linux-imx@nxp.com, gregkh@linuxfoundation.org, mripard@kernel.org, paul.kocialkowski@bootlin.com, wens@csie.org, jernej.skrabec@siol.net, peng.fan@nxp.com, hverkuil-cisco@xs4all.nl, dan.carpenter@oracle.com Cc: linux-media@vger.kernel.org, linux-rockchip@lists.infradead.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kernel@collabora.com, Benjamin Gaignard Subject: [PATCH v4 05/11] media: hantro: Add a field to distinguish the hardware versions Date: Wed, 3 Mar 2021 12:39:46 +0100 Message-Id: <20210303113952.178519-6-benjamin.gaignard@collabora.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210303113952.178519-1-benjamin.gaignard@collabora.com> References: <20210303113952.178519-1-benjamin.gaignard@collabora.com> MIME-Version: 1.0 Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org Decoders hardware blocks could exist in multiple versions: add a field to distinguish them at runtime. G2 hardware block doesn't have postprocessor hantro_needs_postproc function should always returns false in for this hardware. hantro_needs_postproc function becoming to much complex to stay inline in .h file move it to .c file. Keep the default behavoir to be G1 hardware. Signed-off-by: Benjamin Gaignard --- drivers/staging/media/hantro/hantro.h | 13 +++++++------ drivers/staging/media/hantro/hantro_drv.c | 2 ++ drivers/staging/media/hantro/hantro_postproc.c | 17 +++++++++++++++++ 3 files changed, 26 insertions(+), 6 deletions(-) diff --git a/drivers/staging/media/hantro/hantro.h b/drivers/staging/media/hantro/hantro.h index a76a0d79db9f..05876e426419 100644 --- a/drivers/staging/media/hantro/hantro.h +++ b/drivers/staging/media/hantro/hantro.h @@ -37,6 +37,9 @@ struct hantro_codec_ops; #define HANTRO_HEVC_DECODER BIT(19) #define HANTRO_DECODERS 0xffff0000 +#define HANTRO_G1_REV 0x6731 +#define HANTRO_G2_REV 0x6732 + /** * struct hantro_irq - irq handler and name * @@ -171,6 +174,7 @@ hantro_vdev_to_func(struct video_device *vdev) * @enc_base: Mapped address of VPU encoder register for convenience. * @dec_base: Mapped address of VPU decoder register for convenience. * @ctrl_base: Mapped address of VPU control block. + * @core_hw_dec_rev Runtime detected HW decoder core revision * @vpu_mutex: Mutex to synchronize V4L2 calls. * @irqlock: Spinlock to synchronize access to data structures * shared with interrupt handlers. @@ -190,6 +194,7 @@ struct hantro_dev { void __iomem *enc_base; void __iomem *dec_base; void __iomem *ctrl_base; + u32 core_hw_dec_rev; struct mutex vpu_mutex; /* video_device lock */ spinlock_t irqlock; @@ -412,12 +417,8 @@ hantro_get_dst_buf(struct hantro_ctx *ctx) return v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx); } -static inline bool -hantro_needs_postproc(const struct hantro_ctx *ctx, - const struct hantro_fmt *fmt) -{ - return !ctx->is_encoder && fmt->fourcc != V4L2_PIX_FMT_NV12; -} +bool hantro_needs_postproc(const struct hantro_ctx *ctx, + const struct hantro_fmt *fmt); static inline dma_addr_t hantro_get_dec_buf_addr(struct hantro_ctx *ctx, struct vb2_buffer *vb) diff --git a/drivers/staging/media/hantro/hantro_drv.c b/drivers/staging/media/hantro/hantro_drv.c index f0b68e16fcc0..e3e6df28f470 100644 --- a/drivers/staging/media/hantro/hantro_drv.c +++ b/drivers/staging/media/hantro/hantro_drv.c @@ -836,6 +836,8 @@ static int hantro_probe(struct platform_device *pdev) } vpu->enc_base = vpu->reg_bases[0] + vpu->variant->enc_offset; vpu->dec_base = vpu->reg_bases[0] + vpu->variant->dec_offset; + /* by default decoder is G1 */ + vpu->core_hw_dec_rev = HANTRO_G1_REV; ret = dma_set_coherent_mask(vpu->dev, DMA_BIT_MASK(32)); if (ret) { diff --git a/drivers/staging/media/hantro/hantro_postproc.c b/drivers/staging/media/hantro/hantro_postproc.c index 6d2a8f2a8f0b..050880f720d6 100644 --- a/drivers/staging/media/hantro/hantro_postproc.c +++ b/drivers/staging/media/hantro/hantro_postproc.c @@ -50,6 +50,23 @@ const struct hantro_postproc_regs hantro_g1_postproc_regs = { .display_width = {G1_REG_PP_DISPLAY_WIDTH, 0, 0xfff}, }; +bool hantro_needs_postproc(const struct hantro_ctx *ctx, + const struct hantro_fmt *fmt) +{ + struct hantro_dev *vpu = ctx->dev; + + if (ctx->is_encoder) + return false; + + if (vpu->core_hw_dec_rev == HANTRO_G1_REV) + return fmt->fourcc != V4L2_PIX_FMT_NV12; + + if (vpu->core_hw_dec_rev == HANTRO_G2_REV) + return false; + + return false; +} + void hantro_postproc_enable(struct hantro_ctx *ctx) { struct hantro_dev *vpu = ctx->dev;