diff mbox series

[v2,08/12] ARM: dts: rockchip: add power controller for RK3036

Message ID 20210527154455.358869-9-knaerzche@gmail.com (mailing list archive)
State New, archived
Headers show
Series Add support for older Rockchip SoCs to V4L2 hantro and rkvdec drivers | expand

Commit Message

Alex Bee May 27, 2021, 3:44 p.m. UTC
Add the power controller node and the correspondending qos nodes for
RK3036.
Also add the power-domain property to the nodes that are already
present.
Note: Since the regiser offsets of the axi interconnect QoS are missing
in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel.

Signed-off-by: Alex Bee <knaerzche@gmail.com>
---

 Changes in v2:
 - moved power-domains property after iommus-property

 arch/arm/boot/dts/rk3036.dtsi | 51 +++++++++++++++++++++++++++++++++++
 1 file changed, 51 insertions(+)

Comments

Ezequiel Garcia June 11, 2021, 3:58 p.m. UTC | #1
Hi Heiko,

On Thu, 2021-05-27 at 17:44 +0200, Alex Bee wrote:
> Add the power controller node and the correspondending qos nodes for
> RK3036.
> Also add the power-domain property to the nodes that are already
> present.
> Note: Since the regiser offsets of the axi interconnect QoS are missing
> in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel.
> 

Can you take care of the device tree changes (patches 8 to 12)?

Thanks!
Ezequiel
Heiko Stuebner June 13, 2021, 4:22 p.m. UTC | #2
Am Freitag, 11. Juni 2021, 17:58:58 CEST schrieb Ezequiel Garcia:
> Hi Heiko,
> 
> On Thu, 2021-05-27 at 17:44 +0200, Alex Bee wrote:
> > Add the power controller node and the correspondending qos nodes for
> > RK3036.
> > Also add the power-domain property to the nodes that are already
> > present.
> > Note: Since the regiser offsets of the axi interconnect QoS are missing
> > in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel.
> > 
> 
> Can you take care of the device tree changes (patches 8 to 12)?

sure, I'll pick the power-domains now but need to wait for
the vpu nodes for the driver parts to land in the media tree.


Heiko
Alex Bee June 21, 2021, 11:58 a.m. UTC | #3
Hi Heiko,

Am 13.06.21 um 18:22 schrieb Heiko Stuebner:
> Am Freitag, 11. Juni 2021, 17:58:58 CEST schrieb Ezequiel Garcia:
>> Hi Heiko,
>>
>> On Thu, 2021-05-27 at 17:44 +0200, Alex Bee wrote:
>>> Add the power controller node and the correspondending qos nodes for
>>> RK3036.
>>> Also add the power-domain property to the nodes that are already
>>> present.
>>> Note: Since the regiser offsets of the axi interconnect QoS are missing
>>> in the TRM (RK3036 TRM V1.0), they have been taken from vendor kernel.
>>>
>> Can you take care of the device tree changes (patches 8 to 12)?
> sure, I'll pick the power-domains now but need to wait for
> the vpu nodes for the driver parts to land in the media tree.

Looks like I'm too late for 5.14 - just in case you didn't follow or 
didn't receive a notification:

hantro patches of this series have been merged in media_tree and vpu 
node patches (please pick from v2) could get reviewed/applied now.

Thanks,

Alex

>
> Heiko
>
>
diff mbox series

Patch

diff --git a/arch/arm/boot/dts/rk3036.dtsi b/arch/arm/boot/dts/rk3036.dtsi
index 9ccefa8282ba..76ab663eccf7 100644
--- a/arch/arm/boot/dts/rk3036.dtsi
+++ b/arch/arm/boot/dts/rk3036.dtsi
@@ -6,6 +6,7 @@ 
 #include <dt-bindings/pinctrl/rockchip.h>
 #include <dt-bindings/clock/rk3036-cru.h>
 #include <dt-bindings/soc/rockchip,boot-mode.h>
+#include <dt-bindings/power/rk3036-power.h>
 
 / {
 	#address-cells = <1>;
@@ -111,6 +112,7 @@  gpu: gpu@10090000 {
 		assigned-clock-rates = <100000000>;
 		clocks = <&cru SCLK_GPU>, <&cru SCLK_GPU>;
 		clock-names = "bus", "core";
+		power-domains = <&power RK3036_PD_GPU>;
 		resets = <&cru SRST_GPU>;
 		status = "disabled";
 	};
@@ -124,6 +126,7 @@  vop: vop@10118000 {
 		resets = <&cru SRST_LCDC1_A>, <&cru SRST_LCDC1_H>, <&cru SRST_LCDC1_D>;
 		reset-names = "axi", "ahb", "dclk";
 		iommus = <&vop_mmu>;
+		power-domains = <&power RK3036_PD_VIO>;
 		status = "disabled";
 
 		vop_out: port {
@@ -142,10 +145,26 @@  vop_mmu: iommu@10118300 {
 		interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
 		clocks = <&cru ACLK_LCDC>, <&cru HCLK_LCDC>;
 		clock-names = "aclk", "iface";
+		power-domains = <&power RK3036_PD_VIO>;
 		#iommu-cells = <0>;
 		status = "disabled";
 	};
 
+	qos_gpu: qos@1012d000 {
+		compatible = "rockchip,rk3036-qos", "syscon";
+		reg = <0x1012d000 0x20>;
+	};
+
+	qos_vpu: qos@1012e000 {
+		compatible = "rockchip,rk3036-qos", "syscon";
+		reg = <0x1012e000 0x20>;
+	};
+
+	qos_vio: qos@1012f000 {
+		compatible = "rockchip,rk3036-qos", "syscon";
+		reg = <0x1012f000 0x20>;
+	};
+
 	gic: interrupt-controller@10139000 {
 		compatible = "arm,gic-400";
 		interrupt-controller;
@@ -301,6 +320,38 @@  grf: syscon@20008000 {
 		compatible = "rockchip,rk3036-grf", "syscon", "simple-mfd";
 		reg = <0x20008000 0x1000>;
 
+		power: power-controller {
+			compatible = "rockchip,rk3036-power-controller";
+			#power-domain-cells = <1>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			power-domain@RK3036_PD_VIO {
+				reg = <RK3036_PD_VIO>;
+				clocks = <&cru ACLK_LCDC>,
+					 <&cru HCLK_LCDC>,
+					 <&cru SCLK_LCDC>;
+				pm_qos = <&qos_vio>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3036_PD_VPU {
+				reg = <RK3036_PD_VPU>;
+				clocks = <&cru ACLK_VCODEC>,
+					 <&cru HCLK_VCODEC>;
+				pm_qos = <&qos_vpu>;
+				#power-domain-cells = <0>;
+			};
+
+			power-domain@RK3036_PD_GPU {
+				reg = <RK3036_PD_GPU>;
+				clocks = <&cru SCLK_GPU>;
+				pm_qos = <&qos_gpu>;
+				#power-domain-cells = <0>;
+			};
+
+		};
+
 		reboot-mode {
 			compatible = "syscon-reboot-mode";
 			offset = <0x1d8>;