From patchwork Wed Jul 14 13:38:46 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 12376963 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.6 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 82E4CC11F6B for ; Wed, 14 Jul 2021 13:38:56 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 67EC6613C8 for ; Wed, 14 Jul 2021 13:38:56 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232529AbhGNNlq (ORCPT ); Wed, 14 Jul 2021 09:41:46 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:56700 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232116AbhGNNlo (ORCPT ); Wed, 14 Jul 2021 09:41:44 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1626269930; x=1628861930; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=wRClOOTpYIKz17YoQZPGEsQWo4OJcSdhhZ7l/4lJrYw=; b=Y4r2FMILViNSVeD9GPsSSMoef9Qggqvvzu/jrYQ2sUs7fNU93aYIUZgpxBOKysQg +2lpGvVL8/zBqOPoeaqiHYDz7WgNF/GRSecUR58wSaK2o8pkS2wMQFBIyPFrcy6v ol/pjPfMls3c7U1JaoW55E7326N8MqEcOZWQcybP+MA=; X-AuditID: c39127d2-1d8f870000001daf-21-60eee8ea67df Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id DB.57.07599.AE8EEE06; Wed, 14 Jul 2021 15:38:50 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021071415385012-1154290 ; Wed, 14 Jul 2021 15:38:50 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Dirk Bender , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v6 3/6] media: mt9p031: Fix corrupted frame after restarting stream Date: Wed, 14 Jul 2021 15:38:46 +0200 Message-Id: <20210714133849.1041619-4-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210714133849.1041619-1-s.riedmueller@phytec.de> References: <20210714133849.1041619-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:50, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 14.07.2021 15:38:50 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrFLMWRmVeSWpSXmKPExsWyRoCBS/fVi3cJBv8mKVnMP3KO1aJz4hJ2 i8u75rBZ9GzYymqxbNMfJovWvUfYLT5t+cbkwO4xu2Mmq8emVZ1sHvNOBnp83iQXwBLFZZOS mpNZllqkb5fAlfFr+hW2gmsiFYd/2DQwfhboYuTgkBAwkfj2mLeLkYtDSGAbo8ThbxsZIZwL jBKNuzczdzFycrAJGEksmNbIBJIQEWhjlNhxpBnMYRa4xijx/e8DdpAqYYFgiUvH/7GB2CwC qhLtt3rAunkF7CQ+/FoBViMhIC8x89J3MJtTwF6i++g/FhBbCKjmzuX5jBD1ghInZz5hAVkg IXCFUeLuuueMEM1CEqcXnwUbyiygLbFs4WvmCYwCs5D0zEKSWsDItIpRKDczOTu1KDNbryCj siQ1WS8ldRMjMHwPT1S/tIOxb47HIUYmDsZDjBIczEoivEuN3iYI8aYkVlalFuXHF5XmpBYf YpTmYFES593AWxImJJCeWJKanZpakFoEk2Xi4JRqYPTaednvzwmBl/r++2fwZRVyPKz93DRl xXnjydl6m7dvvr/kJ+ePRrX70bEu4VVBbd8ON+/q7Tp+5yB72cGSyY861e9oOB2MnMv0KXd3 6pTd7VeklHm6ONqkXny29Q/49eVAlNGnSdalHbl68yYs/Kj4+45btdK+tzkXvBY8uxDdl7zT t4HjyV8lluKMREMt5qLiRAAPDnT8TQIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Dirk Bender To prevent corrupted frames after starting and stopping the sensor its datasheet specifies a specific pause sequence to follow: Stopping: Set Pause_Restart Bit -> Set Restart Bit -> Set Chip_Enable Off Restarting: Set Chip_Enable On -> Clear Pause_Restart Bit The Restart Bit is cleared automatically and must not be cleared manually as this would cause undefined behavior. Signed-off-by: Dirk Bender Signed-off-by: Stefan Riedmueller --- drivers/media/i2c/mt9p031.c | 28 +++++++++++++++++++++++++++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index ea90aff576ba..ee2777059682 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -79,7 +79,9 @@ #define MT9P031_PIXEL_CLOCK_INVERT (1 << 15) #define MT9P031_PIXEL_CLOCK_SHIFT(n) ((n) << 8) #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0) -#define MT9P031_FRAME_RESTART 0x0b +#define MT9P031_RESTART 0x0b +#define MT9P031_FRAME_PAUSE_RESTART (1 << 1) +#define MT9P031_FRAME_RESTART (1 << 0) #define MT9P031_SHUTTER_DELAY 0x0c #define MT9P031_RST 0x0d #define MT9P031_RST_ENABLE 1 @@ -456,9 +458,23 @@ static int mt9p031_set_params(struct mt9p031 *mt9p031) static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) { struct mt9p031 *mt9p031 = to_mt9p031(subdev); + struct i2c_client *client = v4l2_get_subdevdata(subdev); + int val; int ret; if (!enable) { + /* enable pause restart */ + val = MT9P031_FRAME_PAUSE_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + + /* enable restart + keep pause restart set */ + val |= MT9P031_FRAME_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + /* Stop sensor readout */ ret = mt9p031_set_output_control(mt9p031, MT9P031_OUTPUT_CONTROL_CEN, 0); @@ -478,6 +494,16 @@ static int mt9p031_s_stream(struct v4l2_subdev *subdev, int enable) if (ret < 0) return ret; + /* + * - clear pause restart + * - don't clear restart as clearing restart manually can cause + * undefined behavior + */ + val = MT9P031_FRAME_RESTART; + ret = mt9p031_write(client, MT9P031_RESTART, val); + if (ret < 0) + return ret; + return mt9p031_pll_enable(mt9p031); }