| Message ID | 20210719074640.25058-3-moudy.ho@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | media: mediatek: support mdp3 on mt8183 platform | expand |
Hi Moudy Ho, Thank you for your patch. Missatge de Moudy Ho <moudy.ho@mediatek.com> del dia dl., 19 de jul. 2021 a les 9:47: > > Add device nodes for Media Data Path 3 (MDP3) modules. > > Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > --- > Depend on: > [1] https://lore.kernel.org/patchwork/patch/1164746/ > [2] https://patchwork.kernel.org/patch/11703299/ > [3] https://patchwork.kernel.org/patch/11283773/ I think all these patches are old, some of them already landed in other forms, like the first one. I don't think these dependencies are still valid, so please review and remove them if they are not needed. > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index c5e822b6b77a..30920d6ce7d2 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -1127,6 +1127,112 @@ > mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > }; > > + mdp3_rdma0: mdp3_rdma0@14001000 { > + compatible = "mediatek,mt8183-mdp3", > + "mediatek,mt8183-mdp3-rdma"; > + mediatek,scp = <&scp>; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-dl", "mediatek,mt8183-mdp3-dl", > + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto"; > + mdp3-comp-ids = <0 1 0 1>; > + reg = <0 0x14001000 0 0x1000>, > + <0 0x14000000 0 0x1000>, > + <0 0x15020000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, > + <&gce SUBSYS_1400XXXX 0 0x1000>, > + <&gce SUBSYS_1502XXXX 0 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > + <&mmsys CLK_MM_MDP_RSZ1>, > + <&mmsys CLK_MM_MDP_DL_TXCK>, > + <&mmsys CLK_MM_MDP_DL_RX>, > + <&mmsys CLK_MM_IPU_DL_TXCK>, > + <&mmsys CLK_MM_IPU_DL_RX>; > + iommus = <&iommu M4U_PORT_MDP_RDMA0>; > + mediatek,mmsys = <&mmsys>; > + mediatek,mm-mutex = <&mutex>; > + mediatek,mailbox-gce = <&gce>; > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>; > + mdp3-rsz0 = <&mdp3_rsz0>; /* debug only */ > + mdp3-rsz1 = <&mdp3_rsz1>; /* debug only */ > + mdp3-wrot0 = <&mdp3_wrot0>; /* debug only */ > + mdp3-wdma0 = <&mdp3_wdma>; /* debug only */ > + mdp3-ccorr0 = <&mdp3_ccorr>; /* debug only */ > + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, > + <&gce 0x14010000 SUBSYS_1401XXXX>, > + <&gce 0x14020000 SUBSYS_1402XXXX>, > + <&gce 0x15020000 SUBSYS_1502XXXX>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, > + <CMDQ_EVENT_MDP_RDMA0_EOF>, > + <CMDQ_EVENT_MDP_RSZ0_SOF>, > + <CMDQ_EVENT_MDP_RSZ1_SOF>, > + <CMDQ_EVENT_MDP_TDSHP_SOF>, > + <CMDQ_EVENT_MDP_WROT0_SOF>, > + <CMDQ_EVENT_MDP_WROT0_EOF>, > + <CMDQ_EVENT_MDP_WDMA0_SOF>, > + <CMDQ_EVENT_MDP_WDMA0_EOF>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>, > + <CMDQ_EVENT_WPE_A_DONE>, > + <CMDQ_EVENT_SPE_B_DONE>; > + }; > + > + mdp3_rsz0: mdp3_rsz0@14003000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x14003000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > + }; > + > + mdp3_rsz1: mdp3_rsz1@14004000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + mediatek,mdp3-id = <1>; > + reg = <0 0x14004000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > + }; > + > + mdp3_wrot0: mdp3_wrot0@14005000 { > + compatible = "mediatek,mt8183-mdp3-wrot"; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-path"; > + mdp3-comp-ids = <0>; > + reg = <0 0x14005000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > + iommus = <&iommu M4U_PORT_MDP_WROT0>; > + }; > + > + mdp3_wdma: mdp3_wdma@14006000 { > + compatible = "mediatek,mt8183-mdp3-wdma"; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-path"; > + mdp3-comp-ids = <1>; > + reg = <0 0x14006000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > + iommus = <&iommu M4U_PORT_MDP_WDMA0>; > + }; > + > ovl0: ovl@14008000 { > compatible = "mediatek,mt8183-disp-ovl"; > reg = <0 0x14008000 0 0x1000>; > @@ -1272,6 +1378,14 @@ > clock-names = "apb", "smi", "gals0", "gals1"; > }; > > + mdp3_ccorr: mdp3_ccorr@1401c000 { > + compatible = "mediatek,mt8183-mdp3-ccorr"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x1401c000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > + }; > + > imgsys: syscon@15020000 { > compatible = "mediatek,mt8183-imgsys", "syscon"; > reg = <0 0x15020000 0 0x1000>; > -- > 2.18.0 >
Hi, Moudy: On Mon, 2021-07-19 at 15:46 +0800, Moudy Ho wrote: > Add device nodes for Media Data Path 3 (MDP3) modules. > > Signed-off-by: Ping-Hsun Wu <ping-hsun.wu@mediatek.com> > Signed-off-by: daoyuan huang <daoyuan.huang@mediatek.com> > Signed-off-by: Moudy Ho <moudy.ho@mediatek.com> > --- > Depend on: > [1] https://urldefense.com/v3/__https://lore.kernel.org/patchwork/patch/1164746/__;!!CTRNKA9wMg0ARbw!zIYDSC1kafxhfEfpyIjKYA5S2fo7ND5cvC3uL06yjladpA-22RCjaGcPPqpKhw$ > [2] https://urldefense.com/v3/__https://patchwork.kernel.org/patch/11703299/__;!!CTRNKA9wMg0ARbw!zIYDSC1kafxhfEfpyIjKYA5S2fo7ND5cvC3uL06yjladpA-22RCjaGerzVNylA$ > [3] https://urldefense.com/v3/__https://patchwork.kernel.org/patch/11283773/__;!!CTRNKA9wMg0ARbw!zIYDSC1kafxhfEfpyIjKYA5S2fo7ND5cvC3uL06yjladpA-22RCjaGe4IDGnpQ$ > --- > arch/arm64/boot/dts/mediatek/mt8183.dtsi | 114 +++++++++++++++++++++++ > 1 file changed, 114 insertions(+) > > diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > index c5e822b6b77a..30920d6ce7d2 100644 > --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi > +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi > @@ -1127,6 +1127,112 @@ > mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; > }; > > + mdp3_rdma0: mdp3_rdma0@14001000 { > + compatible = "mediatek,mt8183-mdp3", > + "mediatek,mt8183-mdp3-rdma"; > + mediatek,scp = <&scp>; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-dl", "mediatek,mt8183-mdp3-dl", > + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto"; > + mdp3-comp-ids = <0 1 0 1>; > + reg = <0 0x14001000 0 0x1000>, > + <0 0x14000000 0 0x1000>, > + <0 0x15020000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, > + <&gce SUBSYS_1400XXXX 0 0x1000>, > + <&gce SUBSYS_1502XXXX 0 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_RDMA0>, > + <&mmsys CLK_MM_MDP_RSZ1>, > + <&mmsys CLK_MM_MDP_DL_TXCK>, > + <&mmsys CLK_MM_MDP_DL_RX>, > + <&mmsys CLK_MM_IPU_DL_TXCK>, > + <&mmsys CLK_MM_IPU_DL_RX>; > + iommus = <&iommu M4U_PORT_MDP_RDMA0>; > + mediatek,mmsys = <&mmsys>; > + mediatek,mm-mutex = <&mutex>; > + mediatek,mailbox-gce = <&gce>; > + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>, > + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>; > + mdp3-rsz0 = <&mdp3_rsz0>; /* debug only */ > + mdp3-rsz1 = <&mdp3_rsz1>; /* debug only */ > + mdp3-wrot0 = <&mdp3_wrot0>; /* debug only */ > + mdp3-wdma0 = <&mdp3_wdma>; /* debug only */ > + mdp3-ccorr0 = <&mdp3_ccorr>; /* debug only */ > + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, > + <&gce 0x14010000 SUBSYS_1401XXXX>, > + <&gce 0x14020000 SUBSYS_1402XXXX>, > + <&gce 0x15020000 SUBSYS_1502XXXX>; > + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, > + <CMDQ_EVENT_MDP_RDMA0_EOF>, > + <CMDQ_EVENT_MDP_RSZ0_SOF>, > + <CMDQ_EVENT_MDP_RSZ1_SOF>, RSZ event is sent by rsz device, so move this event into rsz device. > + <CMDQ_EVENT_MDP_TDSHP_SOF>, > + <CMDQ_EVENT_MDP_WROT0_SOF>, > + <CMDQ_EVENT_MDP_WROT0_EOF>, > + <CMDQ_EVENT_MDP_WDMA0_SOF>, > + <CMDQ_EVENT_MDP_WDMA0_EOF>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>, > + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>, > + <CMDQ_EVENT_WPE_A_DONE>, > + <CMDQ_EVENT_SPE_B_DONE>; Ditto for these event. Regards, CK. > + }; > + > + mdp3_rsz0: mdp3_rsz0@14003000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x14003000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ0>; > + }; > + > + mdp3_rsz1: mdp3_rsz1@14004000 { > + compatible = "mediatek,mt8183-mdp3-rsz"; > + mediatek,mdp3-id = <1>; > + reg = <0 0x14004000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_RSZ1>; > + }; > + > + mdp3_wrot0: mdp3_wrot0@14005000 { > + compatible = "mediatek,mt8183-mdp3-wrot"; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-path"; > + mdp3-comp-ids = <0>; > + reg = <0 0x14005000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WROT0>; > + iommus = <&iommu M4U_PORT_MDP_WROT0>; > + }; > + > + mdp3_wdma: mdp3_wdma@14006000 { > + compatible = "mediatek,mt8183-mdp3-wdma"; > + mediatek,mdp3-id = <0>; > + mdp3-comps = "mediatek,mt8183-mdp3-path"; > + mdp3-comp-ids = <1>; > + reg = <0 0x14006000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; > + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; > + clocks = <&mmsys CLK_MM_MDP_WDMA0>; > + iommus = <&iommu M4U_PORT_MDP_WDMA0>; > + }; > + > ovl0: ovl@14008000 { > compatible = "mediatek,mt8183-disp-ovl"; > reg = <0 0x14008000 0 0x1000>; > @@ -1272,6 +1378,14 @@ > clock-names = "apb", "smi", "gals0", "gals1"; > }; > > + mdp3_ccorr: mdp3_ccorr@1401c000 { > + compatible = "mediatek,mt8183-mdp3-ccorr"; > + mediatek,mdp3-id = <0>; > + reg = <0 0x1401c000 0 0x1000>; > + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; > + clocks = <&mmsys CLK_MM_MDP_CCORR>; > + }; > + > imgsys: syscon@15020000 { > compatible = "mediatek,mt8183-imgsys", "syscon"; > reg = <0 0x15020000 0 0x1000>;
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi index c5e822b6b77a..30920d6ce7d2 100644 --- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi +++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi @@ -1127,6 +1127,112 @@ mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>; }; + mdp3_rdma0: mdp3_rdma0@14001000 { + compatible = "mediatek,mt8183-mdp3", + "mediatek,mt8183-mdp3-rdma"; + mediatek,scp = <&scp>; + mediatek,mdp3-id = <0>; + mdp3-comps = "mediatek,mt8183-mdp3-dl", "mediatek,mt8183-mdp3-dl", + "mediatek,mt8183-mdp3-imgi", "mediatek,mt8183-mdp3-exto"; + mdp3-comp-ids = <0 1 0 1>; + reg = <0 0x14001000 0 0x1000>, + <0 0x14000000 0 0x1000>, + <0 0x15020000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x1000 0x1000>, + <&gce SUBSYS_1400XXXX 0 0x1000>, + <&gce SUBSYS_1502XXXX 0 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_RDMA0>, + <&mmsys CLK_MM_MDP_RSZ1>, + <&mmsys CLK_MM_MDP_DL_TXCK>, + <&mmsys CLK_MM_MDP_DL_RX>, + <&mmsys CLK_MM_IPU_DL_TXCK>, + <&mmsys CLK_MM_IPU_DL_RX>; + iommus = <&iommu M4U_PORT_MDP_RDMA0>; + mediatek,mmsys = <&mmsys>; + mediatek,mm-mutex = <&mutex>; + mediatek,mailbox-gce = <&gce>; + mboxes = <&gce 20 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 21 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 22 CMDQ_THR_PRIO_LOWEST 0>, + <&gce 23 CMDQ_THR_PRIO_LOWEST 0>; + mdp3-rsz0 = <&mdp3_rsz0>; /* debug only */ + mdp3-rsz1 = <&mdp3_rsz1>; /* debug only */ + mdp3-wrot0 = <&mdp3_wrot0>; /* debug only */ + mdp3-wdma0 = <&mdp3_wdma>; /* debug only */ + mdp3-ccorr0 = <&mdp3_ccorr>; /* debug only */ + gce-subsys = <&gce 0x14000000 SUBSYS_1400XXXX>, + <&gce 0x14010000 SUBSYS_1401XXXX>, + <&gce 0x14020000 SUBSYS_1402XXXX>, + <&gce 0x15020000 SUBSYS_1502XXXX>; + mediatek,gce-events = <CMDQ_EVENT_MDP_RDMA0_SOF>, + <CMDQ_EVENT_MDP_RDMA0_EOF>, + <CMDQ_EVENT_MDP_RSZ0_SOF>, + <CMDQ_EVENT_MDP_RSZ1_SOF>, + <CMDQ_EVENT_MDP_TDSHP_SOF>, + <CMDQ_EVENT_MDP_WROT0_SOF>, + <CMDQ_EVENT_MDP_WROT0_EOF>, + <CMDQ_EVENT_MDP_WDMA0_SOF>, + <CMDQ_EVENT_MDP_WDMA0_EOF>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_0>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_1>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_2>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_3>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_4>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_5>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_6>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_7>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_8>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_9>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_10>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_11>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_12>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_13>, + <CMDQ_EVENT_ISP_FRAME_DONE_P2_14>, + <CMDQ_EVENT_WPE_A_DONE>, + <CMDQ_EVENT_SPE_B_DONE>; + }; + + mdp3_rsz0: mdp3_rsz0@14003000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <0>; + reg = <0 0x14003000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x3000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ0>; + }; + + mdp3_rsz1: mdp3_rsz1@14004000 { + compatible = "mediatek,mt8183-mdp3-rsz"; + mediatek,mdp3-id = <1>; + reg = <0 0x14004000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x4000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_RSZ1>; + }; + + mdp3_wrot0: mdp3_wrot0@14005000 { + compatible = "mediatek,mt8183-mdp3-wrot"; + mediatek,mdp3-id = <0>; + mdp3-comps = "mediatek,mt8183-mdp3-path"; + mdp3-comp-ids = <0>; + reg = <0 0x14005000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WROT0>; + iommus = <&iommu M4U_PORT_MDP_WROT0>; + }; + + mdp3_wdma: mdp3_wdma@14006000 { + compatible = "mediatek,mt8183-mdp3-wdma"; + mediatek,mdp3-id = <0>; + mdp3-comps = "mediatek,mt8183-mdp3-path"; + mdp3-comp-ids = <1>; + reg = <0 0x14006000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>; + power-domains = <&spm MT8183_POWER_DOMAIN_DISP>; + clocks = <&mmsys CLK_MM_MDP_WDMA0>; + iommus = <&iommu M4U_PORT_MDP_WDMA0>; + }; + ovl0: ovl@14008000 { compatible = "mediatek,mt8183-disp-ovl"; reg = <0 0x14008000 0 0x1000>; @@ -1272,6 +1378,14 @@ clock-names = "apb", "smi", "gals0", "gals1"; }; + mdp3_ccorr: mdp3_ccorr@1401c000 { + compatible = "mediatek,mt8183-mdp3-ccorr"; + mediatek,mdp3-id = <0>; + reg = <0 0x1401c000 0 0x1000>; + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0xc000 0x1000>; + clocks = <&mmsys CLK_MM_MDP_CCORR>; + }; + imgsys: syscon@15020000 { compatible = "mediatek,mt8183-imgsys", "syscon"; reg = <0 0x15020000 0 0x1000>;