From patchwork Mon Jul 26 07:35:13 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: =?utf-8?q?Stefan_Riedm=C3=BCller?= X-Patchwork-Id: 12398749 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.5 required=3.0 tests=BAYES_00,DKIM_INVALID, DKIM_SIGNED,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44D9EC432BE for ; Mon, 26 Jul 2021 07:35:23 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 2C12460F54 for ; Mon, 26 Jul 2021 07:35:23 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S232482AbhGZGyx (ORCPT ); Mon, 26 Jul 2021 02:54:53 -0400 Received: from mickerik.phytec.de ([195.145.39.210]:56446 "EHLO mickerik.phytec.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232391AbhGZGyv (ORCPT ); Mon, 26 Jul 2021 02:54:51 -0400 DKIM-Signature: v=1; a=rsa-sha256; d=phytec.de; s=a4; c=relaxed/simple; q=dns/txt; i=@phytec.de; t=1627284918; x=1629876918; h=From:Sender:Reply-To:Subject:Date:Message-Id:To:Cc:MIME-Version:Content-Type: Content-Transfer-Encoding:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:In-Reply-To:References:List-Id: List-Help:List-Unsubscribe:List-Subscribe:List-Post:List-Owner:List-Archive; bh=BkdkwmiGogTIJ3tL5zily69sBf7WMKTObrHPm+hw5mQ=; b=WDZlCYzCecUKZykIb5d2M9bgGVyPwJHAdPPyqjIxwf5bKuKOJlKh2mY1kGEfuWmR S9+RjHhJ9DxxTOW3C9wRviqSX0vshV6K26tkZhcfb4fHXDgQYxxF8m7eUh1mCqi3 wL30dwNtCRFTiC03FxjStaC5SnyDmQMtMZ1UDD8zPTw=; X-AuditID: c39127d2-1d8f870000001daf-a2-60fe65b6366f Received: from idefix.phytec.de (Unknown_Domain [172.16.0.10]) by mickerik.phytec.de (PHYTEC Mail Gateway) with SMTP id 93.82.07599.6B56EF06; Mon, 26 Jul 2021 09:35:18 +0200 (CEST) Received: from augenblix2.phytec.de ([172.16.0.56]) by idefix.phytec.de (IBM Domino Release 9.0.1FP7) with ESMTP id 2021072609351843-1233314 ; Mon, 26 Jul 2021 09:35:18 +0200 From: Stefan Riedmueller To: Laurent Pinchart , Mauro Carvalho Chehab , Rob Herring Cc: Enrico Scholz , Stefan Riedmueller , Sakari Ailus , linux-media@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v7 1/6] media: mt9p031: Read back the real clock rate Date: Mon, 26 Jul 2021 09:35:13 +0200 Message-Id: <20210726073518.2167398-2-s.riedmueller@phytec.de> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20210726073518.2167398-1-s.riedmueller@phytec.de> References: <20210726073518.2167398-1-s.riedmueller@phytec.de> MIME-Version: 1.0 X-MIMETrack: Itemize by SMTP Server on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 26.07.2021 09:35:18, Serialize by Router on Idefix/Phytec(Release 9.0.1FP7|August 17, 2016) at 26.07.2021 09:35:18 X-TNEFEvaluated: 1 X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrKLMWRmVeSWpSXmKPExsWyRoCBS3db6r8Eg8O7jSzmHznHarH32AUW i86JS9gtLu+aw2bRs2Erq8WyTX+YLFr3HmG3+LTlG5MDh8fsjpmsHptWdbJ5zDsZ6LFi5X8m j8+b5AJYo7hsUlJzMstSi/TtErgyJjV9Zi84xF/xc+J1pgbGDt4uRk4OCQETiZ/Xu1m7GLk4 hAS2MUr8OLiCCcK5wChx8PAiZpAqNgEjiQXTGsESIgJtjBI7jjSDOcwCTxklHtx6yA5SJSzg KvFp0lvGLkYODhYBVYkZs6RBwrwCdhKb/95hglgnLzHz0newck4Be4lbT9+D2UJANa2dG9kh 6gUlTs58wgIyX0LgCqPEyvYTLBDNQhKnF58Fu4hZQFti2cLXzBMYBWYh6ZmFJLWAkWkVo1Bu ZnJ2alFmtl5BRmVJarJeSuomRmBQH56ofmkHY98cj0OMTByMhxglOJiVRHgdVvxOEOJNSays Si3Kjy8qzUktPsQozcGiJM67gbckTEggPbEkNTs1tSC1CCbLxMEp1cBYf9L/Zopd8Il992rv zXosai/Qdyg4+Y+10rkDnEv2FE+qME28mvHu7Ta19Uun9rXOUl3z1j9MJ+SHoW8yl2eakmtB 8LWVATdX6AbX2r65tKx7Y5qPsdiTfvcblj9WuDqXPYt5ftTGofXJJ4ZGC3Xr0uh9/Z8luXhf fSysZEtbsemH9jEx729KLMUZiYZazEXFiQCE3ongWAIAAA== Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org From: Enrico Scholz The real and requested clock can differ and because it is used to calculate PLL values, the real clock rate should be read. Signed-off-by: Enrico Scholz Signed-off-by: Stefan Riedmueller Reviewed-by: Laurent Pinchart --- drivers/media/i2c/mt9p031.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/drivers/media/i2c/mt9p031.c b/drivers/media/i2c/mt9p031.c index 6eb88ef99783..9dea7c813852 100644 --- a/drivers/media/i2c/mt9p031.c +++ b/drivers/media/i2c/mt9p031.c @@ -229,6 +229,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) struct i2c_client *client = v4l2_get_subdevdata(&mt9p031->subdev); struct mt9p031_platform_data *pdata = mt9p031->pdata; + unsigned long ext_freq; int ret; mt9p031->clk = devm_clk_get(&client->dev, NULL); @@ -239,13 +240,15 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) if (ret < 0) return ret; + ext_freq = clk_get_rate(mt9p031->clk); + /* If the external clock frequency is out of bounds for the PLL use the * pixel clock divider only and disable the PLL. */ - if (pdata->ext_freq > limits.ext_clock_max) { + if (ext_freq > limits.ext_clock_max) { unsigned int div; - div = DIV_ROUND_UP(pdata->ext_freq, pdata->target_freq); + div = DIV_ROUND_UP(ext_freq, pdata->target_freq); div = roundup_pow_of_two(div) / 2; mt9p031->clk_div = min_t(unsigned int, div, 64); @@ -254,7 +257,7 @@ static int mt9p031_clk_setup(struct mt9p031 *mt9p031) return 0; } - mt9p031->pll.ext_clock = pdata->ext_freq; + mt9p031->pll.ext_clock = ext_freq; mt9p031->pll.pix_clock = pdata->target_freq; mt9p031->use_pll = true;