From patchwork Fri Oct 15 12:38:28 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Moudy Ho X-Patchwork-Id: 12561351 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 577CFC433FE for ; Fri, 15 Oct 2021 12:39:08 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 3CB2F61090 for ; Fri, 15 Oct 2021 12:39:08 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S235979AbhJOMlM (ORCPT ); Fri, 15 Oct 2021 08:41:12 -0400 Received: from mailgw01.mediatek.com ([60.244.123.138]:57802 "EHLO mailgw01.mediatek.com" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S235537AbhJOMk6 (ORCPT ); Fri, 15 Oct 2021 08:40:58 -0400 X-UUID: 70aebc6bb8ea4edcaf595c89ccb09807-20211015 X-UUID: 70aebc6bb8ea4edcaf595c89ccb09807-20211015 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 219763466; Fri, 15 Oct 2021 20:38:49 +0800 Received: from mtkexhb01.mediatek.inc (172.21.101.102) by mtkmbs10n1.mediatek.inc (172.21.101.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384) id 15.2.792.15; Fri, 15 Oct 2021 20:38:48 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkexhb01.mediatek.inc (172.21.101.102) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 15 Oct 2021 20:38:47 +0800 Received: from mtksdccf07.mediatek.inc (172.21.84.99) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Fri, 15 Oct 2021 20:38:47 +0800 From: Moudy Ho To: , Mauro Carvalho Chehab , "Rob Herring" , Matthias Brugger , "Hans Verkuil" , Jernej Skrabec CC: Maoguang Meng , daoyuan huang , Ping-Hsun Wu , "Geert Uytterhoeven" , Rob Landley , Laurent Pinchart , , , , , , , , , , , , , , , Subject: [PATCH v8 3/7] soc: mediatek: mutex: add support for MDP Date: Fri, 15 Oct 2021 20:38:28 +0800 Message-ID: <20211015123832.17914-4-moudy.ho@mediatek.com> X-Mailer: git-send-email 2.18.0 In-Reply-To: <20211015123832.17914-1-moudy.ho@mediatek.com> References: <20211015123832.17914-1-moudy.ho@mediatek.com> MIME-Version: 1.0 X-MTK: N Precedence: bulk List-ID: X-Mailing-List: linux-media@vger.kernel.org For the purpose of module independence, related settings should be moved from MDP to the corresponding driver. This patch adds more 8183 MDP settings and interface. Signed-off-by: Moudy Ho Acked-By: AngeloGioacchino Del Regno --- drivers/soc/mediatek/mtk-mutex.c | 33 ++++++++++++++++++++++++++ include/linux/soc/mediatek/mtk-mutex.h | 2 ++ 2 files changed, 35 insertions(+) diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c index 2e4bcc300576..adab4c9edc16 100644 --- a/drivers/soc/mediatek/mtk-mutex.c +++ b/drivers/soc/mediatek/mtk-mutex.c @@ -107,6 +107,10 @@ #define MT8183_MUTEX_EOF_DSI0 (MT8183_MUTEX_SOF_DSI0 << 6) #define MT8183_MUTEX_EOF_DPI0 (MT8183_MUTEX_SOF_DPI0 << 6) +#define MT8183_MUTEX_MDP_START 5 +#define MT8183_MUTEX_MDP_MOD_MASK 0x07FFFFFF +#define MT8183_MUTEX_MDP_SOF_MASK 0x00000007 + struct mtk_mutex { int id; bool claimed; @@ -127,6 +131,9 @@ struct mtk_mutex_data { const unsigned int *mutex_sof; const unsigned int mutex_mod_reg; const unsigned int mutex_sof_reg; + const unsigned int *mutex_mdp_offset; + const unsigned int mutex_mdp_mod_mask; + const unsigned int mutex_mdp_sof_mask; const bool no_clk; }; @@ -238,6 +245,14 @@ static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = { [MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0, }; +/* indicate which mutex is used by each pipepline */ +static const unsigned int mt8183_mutex_mdp_offset[MDP_PIPE_MAX] = { + [MDP_PIPE_IMGI] = MT8183_MUTEX_MDP_START, + [MDP_PIPE_RDMA0] = MT8183_MUTEX_MDP_START + 1, + [MDP_PIPE_WPEI] = MT8183_MUTEX_MDP_START + 2, + [MDP_PIPE_WPEI2] = MT8183_MUTEX_MDP_START + 3 +}; + static const struct mtk_mutex_data mt2701_mutex_driver_data = { .mutex_mod = mt2701_mutex_mod, .mutex_sof = mt2712_mutex_sof, @@ -272,6 +287,9 @@ static const struct mtk_mutex_data mt8183_mutex_driver_data = { .mutex_sof = mt8183_mutex_sof, .mutex_mod_reg = MT8183_MUTEX0_MOD0, .mutex_sof_reg = MT8183_MUTEX0_SOF0, + .mutex_mdp_offset = mt8183_mutex_mdp_offset, + .mutex_mdp_mod_mask = MT8183_MUTEX_MDP_MOD_MASK, + .mutex_mdp_sof_mask = MT8183_MUTEX_MDP_SOF_MASK, .no_clk = true, }; @@ -290,6 +308,21 @@ struct mtk_mutex *mtk_mutex_get(struct device *dev) } EXPORT_SYMBOL_GPL(mtk_mutex_get); +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev, + enum mtk_mdp_pipe_id id) +{ + struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev); + int i = mtx->data->mutex_mdp_offset[id]; + + if (!mtx->mutex[i].claimed) { + mtx->mutex[i].claimed = true; + return &mtx->mutex[i]; + } + + return ERR_PTR(-EBUSY); +} +EXPORT_SYMBOL_GPL(mtk_mutex_mdp_get); + void mtk_mutex_put(struct mtk_mutex *mutex) { struct mtk_mutex_ctx *mtx = container_of(mutex, struct mtk_mutex_ctx, diff --git a/include/linux/soc/mediatek/mtk-mutex.h b/include/linux/soc/mediatek/mtk-mutex.h index 6fe4ffbde290..099ddb025d79 100644 --- a/include/linux/soc/mediatek/mtk-mutex.h +++ b/include/linux/soc/mediatek/mtk-mutex.h @@ -11,6 +11,8 @@ struct device; struct mtk_mutex; struct mtk_mutex *mtk_mutex_get(struct device *dev); +struct mtk_mutex *mtk_mutex_mdp_get(struct device *dev, + enum mtk_mdp_pipe_id id); int mtk_mutex_prepare(struct mtk_mutex *mutex); void mtk_mutex_add_comp(struct mtk_mutex *mutex, enum mtk_ddp_comp_id id);